Abstract: Digital input signals xi and xq are multiplied by an multiplier 31 with a distortion compensation coefficient of a distortion compensation coefficient storage unit 33 and then processed by a modulation/amplification unit 1 for sending in the form of analog output signals Z. The analog output signals Z are fed back for processings by an attenuator 43, a mixer 41, a quadrature demodulator 39, etc., and then fed to subtractors 35i and 35q. The subtractors 35i and 35q find differences (errors) between analog input signals Xi and Xq and analog feedback signals Yi and Yq, respectively, and feeds the analog error signals to ADCs 36i and 36q, respectively. The ADCs 36i and 36q convert the analog error signals into digital signals and feeds the digital signals to a distortion compensation coefficient arithmetic unit 5. The distortion compensation coefficient arithmetic unit 5 figures out a new distortion compensation coefficient to update the distortion compensation coefficient storage unit 33.

Abstract: Digital input signals xi and xq are multiplied by an multiplier 31 with a distortion compensation coefficient of a distortion compensation coefficient storage unit 33 and then processed by a modulation/amplification unit 1 for sending in the form of analog output signals Z. The analog output signals Z are fed back for processings by an attenuator 43, a mixer 41, a quadrature demodulator 39, etc., and then fed to subtractors 35i and 35q. The subtractors 35i and 35q find differences (errors) between analog input signals Xi and Xq and analog feedback signals Yi and Yq, respectively, and feeds the analog error signals to ADCs 36i and 36q, respectively. The ADCs 36i and 36q convert the analog error signals into digital signals and feeds the digital signals to a distortion compensation coefficient arithmetic unit 5. The distortion compensation coefficient arithmetic unit 5 figures out a new distortion compensation coefficient to update the distortion compensation coefficient storage unit 33.