Patents by Inventor Takushi Motoyama

Takushi Motoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6553274
    Abstract: A reticle is designed with a method including generating first dummy patterns with intervals from main patterns. Each of the first dummy patterns are divided into a plurality of spaced apart second dummy patterns and then each of the second dummy patterns are measured to find third dummy patterns having widths and areas below smallest allowable values. The third dummy patterns are then respectively connected to second dummy patterns which are adjacent to the third dummy patterns by generating a connecting dummy pattern. Selective non-connected third dummy patterns are removed. The first dummy patterns are divided into a plurality of second dummy patterns by vertical and horizontal strip lines crossing the first dummy patterns.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: April 22, 2003
    Assignee: Fujitsu Limited
    Inventors: Takushi Motoyama, Hideki Harada, Takayuki Tsuru
  • Patent number: 6099992
    Abstract: A reticle is designed with a method including a step of generating first dummy patterns with intervals from main patterns. Each of the first dummy patterns are divided into a plurality of spaced apart second dummy patterns and then each of the second dummy patterns are measured to find third dummy patterns having widths and areas below smallest allowable values. The third dummy patterns are then respectively connected to second dummy patterns which are adjacent to the third dummy patters by generating a connecting dummy pattern. Selective non-connected third dummy patterns are removed. The first dummy patterns are divided into a plurality of second dummy patterns by vertical and horizontal strip lines crossing the first dummy patterns.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: August 8, 2000
    Assignee: Fujitsu Limited
    Inventors: Takushi Motoyama, Hideki Harada, Takayuki Tsuru
  • Patent number: 5621246
    Abstract: A multichip substrate including a bonding pad, wiring layers insulated by polyimide layers and structure for protecting separation or the polyimide layers from occurring due to water oozing from the polyimide layers by: fabricating posts between the bonding pad and an inorganic insulation layer fabricated on a base substrate through the organic insulation layers by accumulating parts of the wiring layers; and providing holes for setting the water free, around the bonding pad so that the polyimide layer is exposed out of the multichip substrate; or fabricating the bonding pad directly on the inorganic insulation layer, fabricating the polyimide layers and wiring layers in terraced configuration at a periphery of the bonding pad.
    Type: Grant
    Filed: March 24, 1994
    Date of Patent: April 15, 1997
    Assignee: Fujitsu Limited
    Inventor: Takushi Motoyama
  • Patent number: 5403438
    Abstract: A process for forming a pattern, which includes forming a first resist layer on an article to be fabricated, which article is formed over a substrate, forming a mask layer of Spin On Glass, for etching the first resist layer, on the first resist layer, patterning the mask layer, selectively etching the first resist layer by using the mask layer as a mask, removing the patterned mask layer, by an etching process, selectively etching the article to be fabricated by using the etched first resist layer as a mask, and removing the etched first resist layer to thus form a predetermined pattern.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: April 4, 1995
    Assignee: Fujitsu Limited
    Inventor: Takushi Motoyama
  • Patent number: 5194364
    Abstract: Process for the formation of resist patterns in a single layer resist process and a two layer resist process comprising using a resist material prepared from a silicon-containing polymer and an addition agent which can bond to said polymer upon an addition reaction when said resist material is exposed to a patterning radiation, and developing an exposed layer of said resist material with the down flow etching. The resulting resist patterns can be advantageously used in the production of LSIs, VLSIs and other devices.
    Type: Grant
    Filed: August 8, 1991
    Date of Patent: March 16, 1993
    Assignee: Fujitsu Limited
    Inventors: Naomichi Abe, Takushi Motoyama
  • Patent number: 5160404
    Abstract: A method for removing a patterned multilevel resist formed on a substrate where layer of a substrate, the multilevel resist has a lower resist layer and an upper resist layer formed on the lower resist layer, and where the upper resist layer contains silicon atoms. The method includes forming a resin layer on the lower resist layer and on a surface exposed from the patterned multilevel resist, and etching the resin layer and the patterned multilevel resist by a first dry etching process using halogen containing gas until the upper resist layer is removed. The resin layer and the multilevel resist, which have remained after the first dry etching process, are etched by a second dry etching process using oxygen containing gas.
    Type: Grant
    Filed: December 5, 1990
    Date of Patent: November 3, 1992
    Assignee: Fujitsu Limited
    Inventor: Takushi Motoyama
  • Patent number: 5030316
    Abstract: A trench etching process comprises the steps of: preparing a substrate, forming a mask pattern for the trench etching having a material different from that of the substrate, on the substrate, and detecting changes in results of emission spectroanalyses generated by etching the mask pattern and the substrate while using the etching ratios of the mask pattern and the silicon substrate to determine that the trench etching is completed.
    Type: Grant
    Filed: January 8, 1990
    Date of Patent: July 9, 1991
    Assignee: Fujitsu Limited
    Inventors: Takushi Motoyama, Naomichi Abe, Satoru Mihara
  • Patent number: 4983543
    Abstract: A method of manufacturing a semiconductor integrated circuit comprises steps of forming at least one semiconductor device on a substrate, depositing an insulator layer on the substrate so as to bury the semiconductor device, providing a contact hole through the insulator layer for exposing a desired part of the semiconductor device, filling the contact hole by a refractory metal for electrical connection, covering the insulator layer by a second insulator layer, forming a groove through the second insulator layer according to a predetermined interconnection pattern such that the groove passes at least one contact hole and such that a top surface of the refractory metal filling the contact hole and a top surface of the first insulator layer are exposed by the groove, forming a material layer acting as nuclei for crystal growth of a second refractory metal at a bottom of the groove substantially continuously along the groove, and depositing the second refractory metal in the groove until the groove is substanti
    Type: Grant
    Filed: September 1, 1989
    Date of Patent: January 8, 1991
    Assignee: Fujitsu Limited
    Inventors: Yasuhisa Sato, Takushi Motoyama