Patents by Inventor Takuya Hirohashi

Takuya Hirohashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10700213
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: June 30, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Takuya Hirohashi, Hideyuki Kishida
  • Patent number: 10461099
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
  • Patent number: 10418491
    Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 17, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Patent number: 10403763
    Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Junichiro Sakata, Takuya Hirohashi, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga
  • Patent number: 10374030
    Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Masashi Oota
  • Patent number: 10355136
    Abstract: In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The semiconductor device includes a gate electrode over an insulating surface; an oxide semiconductor film overlapping with the gate electrode; a gate insulating film that is between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with a surface of the oxide semiconductor film that is an opposite side of a surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film. The spin density of the gate insulating film or the protective film measured by electron spin resonance spectroscopy is lower than 1×1018 spins/cm3, preferably higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: July 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka, Motoki Nakashima, Masahiro Takahashi, Shunsuke Adachi, Takuya Hirohashi
  • Publication number: 20190214499
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: Junichiro SAKATA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Patent number: 10249876
    Abstract: A lithium-ion secondary battery with high capacity is provided. Alternatively, a lithium-ion secondary battery with unproved cycle characteristics is provided. To achieve this, an active material including a particle having a cleavage plane and a layer containing carbon covering at least part of the cleavage plane is provided. The particle having the cleavage plane contains lithium, manganese, nickel, and oxygen. The layer containing carbon preferably contains graphene. When a lithium-ion secondary battery is fabricated using an electrode including the particle having the cleavage plane at least part of which is covered with the layer containing carbon as an active material, the discharge capacity can be increased and the cycle characteristics can be improved.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Kawakami, Tatsuya Ikenuma, Teruaki Ochiai, Shuhei Yoshitomi, Mako Motoyoshi, Hiroyuki Miyake, Yohei Momma, Takuya Hirohashi, Satoshi Seo
  • Patent number: 10236391
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Takuya Hirohashi, Hideyuki Kishida
  • Patent number: 10164180
    Abstract: According to one embodiment, a variable resistance element includes first and second conductive layers and a first layer. The first conductive layer includes at least one of silver, copper, zinc, titanium, vanadium, chrome, manganese, iron, cobalt, nickel, tellurium, or bismuth. The second conductive layer includes at least one of platinum, gold, iridium, tungsten, palladium, rhodium, titanium nitride, or silicon. The first layer includes oxygen and silicon and is provided between the first conductive layer and the second conductive layer. The first layer includes a plurality of holes. The holes are smaller than a thickness of the first layer along a first direction. The first direction is from the second conductive layer toward the first conductive layer. The first layer does not include carbon, or a composition ratio of carbon included in the first layer to silicon included in the first layer is less than 0.1.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: December 25, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiromichi Kuriyama, Yuya Matsubara, Kazunori Harada, Takuya Hirohashi, Harumi Seki, Masumi Saitoh
  • Publication number: 20180366726
    Abstract: To increase capacity per weight of a power storage device, a particle includes a first region, a second region in contact with at least part of a surface of the first region and located on the outside of the first region, and a third region in contact with at least part of a surface of the second region and located on the outside of the second region. The first and the second regions contain lithium and oxygen. At least one of the first region and the second region contains manganese. At least one of the first and the second regions contains an element M. The first region contains a first crystal having a layered rock-salt structure. The second region contains a second crystal having a layered rock-salt structure. An orientation of the first crystal is different from an orientation of the second crystal.
    Type: Application
    Filed: August 28, 2018
    Publication date: December 20, 2018
    Inventors: Takahiro KAWAKAMI, Teruaki OCHIAI, Shuhei YOSHITOMI, Takuya HIROHASHI, Mako MOTOYOSHI, Yohei MOMMA, Junya GOTO
  • Patent number: 10141425
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
  • Publication number: 20180323220
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Application
    Filed: July 2, 2018
    Publication date: November 8, 2018
    Inventors: Masahiro TAKAHASHI, Takuya HIROHASHI, Masashi TSUBUKU, Noritaka ISHIHARA, Masashi OOTA
  • Patent number: 10121903
    Abstract: A semiconductor device including a transistor having a reduced number of oxygen vacancies in a channel formation region of an oxide semiconductor with stable electrical characteristics or high reliability is provided. A gate insulating film is formed over a gate electrode; an oxide semiconductor layer is formed over the gate insulating film; an oxide layer is formed over the oxide semiconductor layer by a sputtering method to form an stacked-layer oxide film including the oxide semiconductor layer and the oxide layer; the stacked-layer oxide film is processed into a predetermined shape; a conductive film containing Ti as a main component is formed over the stacked-layer oxide film; the conductive film is etched to form source and drain electrodes and a depression portion on a back channel side; and portions of the stacked-layer oxide film in contact with the source and drain electrodes are changed to an n-type by heat treatment.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasutaka Nakazawa, Masami Jintyou, Junichi Koezuka, Kenichi Okazaki, Takuya Hirohashi, Shunsuke Adachi
  • Patent number: 10115831
    Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Publication number: 20180286986
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.
    Type: Application
    Filed: May 31, 2018
    Publication date: October 4, 2018
    Inventors: Junichiro SAKATA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Patent number: 10084186
    Abstract: To increase capacity per weight of a power storage device, a particle includes a first region, a second region in contact with at least part of a surface of the first region and located on the outside of the first region, and a third region in contact with at least part of a surface of the second region and located on the outside of the second region. The first and the second regions contain lithium and oxygen. At least one of the first region and the second region contains manganese. At least one of the first and the second regions contains an element M. The first region contains a first crystal having a layered rock-salt structure. The second region contains a second crystal having a layered rock-salt structure. An orientation of the first crystal is different from an orientation of the second crystal.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: September 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Kawakami, Teruaki Ochiai, Shuhei Yoshitomi, Takuya Hirohashi, Mako Motoyoshi, Yohei Momma, Junya Goto
  • Publication number: 20180226510
    Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Patent number: 10026966
    Abstract: A lithium secondary battery which has high charge-discharge capacity, can be charged and discharged at high speed, and has little deterioration in battery characteristics due to charge and discharge is provided. A negative electrode includes a current collector and a negative electrode active material layer. The current collector includes a plurality of protrusion portions extending in a substantially perpendicular direction and a base portion connected to the plurality of protrusion portions. The protrusion portions and the base portion are formed using the same material containing titanium. A top surface of the base portion and at least a side surface of the protrusion portion are covered with the negative electrode active material layer. The negative electrode active material layer may be covered with graphene.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: July 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Ryota Tajima, Teppei Oguni, Takeshi Osada, Shunpei Yamazaki, Shunsuke Adachi, Takuya Hirohashi
  • Publication number: 20180175210
    Abstract: In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The semiconductor device includes a gate electrode over an insulating surface; an oxide semiconductor film overlapping with the gate electrode; a gate insulating film that is between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with a surface of the oxide semiconductor film that is an opposite side of a surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film. The spin density of the gate insulating film or the protective film measured by electron spin resonance spectroscopy is lower than 1×1018 spins/cm3, preferably higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Inventors: Akiharu MIYANAGA, Yasuharu HOSAKA, Toshimitsu OBONAI, Junichi KOEZUKA, Motoki NAKASHIMA, Masahiro TAKAHASHI, Shunsuke ADACHI, Takuya HIROHASHI