Patents by Inventor Takuya Kouya

Takuya Kouya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9445535
    Abstract: A high-frequency module includes a substrate, an integrated circuit mounted to the substrate, a cylindrical shield enclosing the integrated circuit to block radio waves, a casing provided on an opposite side of the substrate relative to the shield to block radio waves, and a choke portion provided in an inner wall of the casing, the inner wall being opposed to the shield, or provided in the substrate, with a predetermined gap being formed relative to the shield, to create an antiphase in radio waves having a predetermined frequency emitted from the integrated circuit into a space above the substrate.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: September 13, 2016
    Assignee: DENSO CORPORATION
    Inventors: Takuya Kouya, Masanobu Yukumatsu, Asahi Kondo
  • Publication number: 20150289419
    Abstract: A high-frequency module includes a substrate, an integrated circuit mounted to the substrate, a cylindrical shield enclosing the integrated circuit to block radio waves, a casing provided on an opposite side of the substrate relative to the shield to block radio waves, and a choke portion provided in an inner wall of the casing, the inner wall being opposed to the shield, or provided in the substrate, with a predetermined gap being formed relative to the shield, to create an antiphase in radio waves having a predetermined frequency emitted from the integrated circuit into a space above the substrate.
    Type: Application
    Filed: November 5, 2013
    Publication date: October 8, 2015
    Applicant: DENSO CORPORATION
    Inventors: Takuya Kouya, Masanobu Yukumatsu, Asahi Kondo
  • Patent number: 8471775
    Abstract: The array antenna includes a feed line, and a plurality of radiating element sections arranged at a predetermined arranging interval in a first direction, each of the radiating element sections including at least one radiating element fed a traveling wave through the feed line. The inter-element line length as a length of the feed line between each succeeding two of the radiating element sections is longer than the arranging interval in the first direction.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: June 25, 2013
    Assignee: Denso Corporation
    Inventors: Kento Nakabayashi, Kazuma Natsume, Yuu Watanabe, Takuya Kouya
  • Patent number: 8247702
    Abstract: An integrated circuit mounted board includes a printed wiring board and an integrated circuit bare chip mounted on the printed wiring board. The printed wiring board includes a metal base, an insulating member made of an insulating material and disposed on the metal base, and a wiring pattern disposed on the insulating member. The wiring pattern includes an electrode part to which the integrated circuit bare chip is electrically coupled. The insulating member includes an under region being opposite to the electrode part. The metal base includes a metal substrate and a metal portion protruding from the metal substrate. The metal portion is buried in the under region of the insulating member.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: August 21, 2012
    Assignee: Denso Corporation
    Inventor: Takuya Kouya
  • Publication number: 20100238067
    Abstract: The array antenna includes a feed line, and a plurality of radiating element sections arranged at a predetermined arranging interval in a first direction, each of the radiating element sections including at least one radiating element fed a traveling wave through the feed line. The inter-element line length as a length of the feed line between each succeeding two of the radiating element sections is longer than the arranging interval in the first direction.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 23, 2010
    Applicant: DENSO CORPORATION
    Inventors: Kento Nakabayashi, Kazuma Natsume, Yuu Watanabe, Takuya Kouya
  • Publication number: 20100226110
    Abstract: A printed IC board has a multilayer printed wiring board and one or more bare IC chips. The multilayer printed wiring board has insulation layers made of PTFE, and wiring patterns formed on the insulation layers which are stacked to make a lamination structure. Electrode parts as parts of the wiring patterns are electrically connected to the bare IC chip. A copper member which serves as a reinforcing member is laid in a region formed in the insulation layers other than a first insulation layer. the region is formed directly below the electrode parts. The region is formed in a direction Z along a thickness of the stacked insulation layers. The region formed directly below the electrode parts in the insulation layers in the insulation layers other than the first insulation layer has a higher rigidity than the insulation layers.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 9, 2010
    Applicant: DENSO CORPORATION
    Inventor: Takuya Kouya
  • Publication number: 20100218985
    Abstract: An integrated circuit mounted board includes a printed wiring board and an integrated circuit bare chip mounted on the printed wiring board. The printed wiring board includes a metal base, an insulating member made of an insulating material and disposed on the metal base, and a wiring pattern disposed on the insulating member. The wiring pattern includes an electrode part to which the integrated circuit bare chip is electrically coupled. The insulating member includes an under region being opposite to the electrode part. The metal base includes a metal substrate and a metal portion protruding from the metal substrate. The metal portion is buried in the under region of the insulating member.
    Type: Application
    Filed: February 9, 2010
    Publication date: September 2, 2010
    Applicant: DENSO CORPORATION
    Inventor: Takuya KOUYA
  • Patent number: 5843849
    Abstract: A first semiconductor layer and a second semiconductor layer are laminated on a semiconductor wafer in that order. A resist pattern having an opening is formed on the second semiconductor layer. The second semiconductor layer is etched through the opening in the formed resist pattern to expose the first semiconductor layer. A surface oxide film is formed on the exposed surface of the first semiconductor layer and then selectively etched away. Alternatively, the exposed surface of the first semiconductor layer is subjected to a separate oxidization treatment and the resulting surface oxide film is selectively removed in the subsequent etching.
    Type: Grant
    Filed: June 13, 1996
    Date of Patent: December 1, 1998
    Assignees: Nippondenso Co., Ltd., Research Development Corporation of Japan
    Inventors: Kouichi Hoshino, Yoshiki Ueno, Takuya Kouya