Patents by Inventor Takuya Matsuo

Takuya Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240166689
    Abstract: An object of the present invention is to provide methods of discovering drugs effective for tough targets, which have conventionally been discovered only with difficulty. The present invention relates to novel methods for cyclizing peptide compounds, and novel peptide compounds and libraries comprising the same, to achieve the above object.
    Type: Application
    Filed: September 1, 2023
    Publication date: May 23, 2024
    Inventors: Shiori KARIYUKI, Takeo IIDA, Miki KOJIMA, Ryuichi TAKEYAMA, Mikimasa TANADA, Tetsuo KOJIMA, Hitoshi IIKURA, Atsushi MATSUO, Takuya SHIRAISHI, Takashi EMURA, Kazuhiko NAKANO, Koji TAKANO, Kousuke ASOU, Takuya TORIZAWA, Ryusuke TAKANO, Nozomi HISADA, Naoaki MURAO, Atsushi OHTA, Kaori KIMURA, Yusuke YAMAGISHI, Tatsuya KATO
  • Publication number: 20240167968
    Abstract: A pair of support sections arranged with a space for placing a sample, a frame supported by the pair of support sections, an irradiation section movably connected to the frame for irradiating radiation, and a detection section movably connected to the frame for detecting radiation scattered by the sample are comprised on a same plane, and the irradiation section and the detection section are movable on the same plane with respect to the frame. Thus, using a space formed between the pair of support sections, it is possible to measure a large sample in a wide range of diffraction angles. Therefore, it is easy to measure the diffraction of the low angle side. Further, since each part is movable on the same plane, it is easy to arrange the parts.
    Type: Application
    Filed: December 10, 2021
    Publication date: May 23, 2024
    Applicant: Rigaku Corporation
    Inventors: Takuya KIKUCHI, Tetsuya OZAWA, Ryuji MATSUO
  • Publication number: 20240140132
    Abstract: An envelope processing apparatus for enclosing an enclosure in an envelope includes an envelope conveyance path, an enclosure supplier, an envelope supplier, a flap opener, and an envelope stacker. The envelope conveyance path extends in a substantially vertical direction to convey the envelope. The enclosure supplier supplies the enclosure to the envelope via the envelope conveyance path. The envelope supplier supplies the envelope to the envelope conveyance path, The flap opener opens a flap portion of the envelope between the envelope supplier and the envelope conveyance path. The envelope stacker stacks the envelope ejected from the envelope conveyance path.
    Type: Application
    Filed: May 6, 2022
    Publication date: May 2, 2024
    Applicant: Ricoh Company, Ltd.
    Inventors: Nobuyoshi SUZUKI, Michitaka SUZUKI, Yuusuke SHIBASAKI, Makoto HIDAKA, Akira KUNIEDA, Takahiro WATANABE, Takuya MORINAGA, Takahiro MATSUDA, Shingo YOSHIZAWA, Shinji ASAMI, Kazuyoshi MATSUO
  • Publication number: 20240128912
    Abstract: A power converter includes: a rectifying and boosting unit that rectifies first alternating-current power supplied from a commercial power supply and boosts a voltage of the first alternating-current power; a capacitor connected to an output end of the rectifying and boosting unit; an inverter to convert power output from the rectifying and boosting unit and the capacitor into second alternating-current power, and output the second alternating-current power to a device; and a control unit that reduces a current flowing through the capacitor by controlling the rectifying and boosting unit and by controlling the inverter such that the inverter outputs, to the device, the second alternating-current power containing a ripple dependent on a ripple of power flowing from the rectifying and boosting unit into the capacitor. The control unit controls operation of the power converter in accordance with an air-conditioning condition of an air conditioner.
    Type: Application
    Filed: February 12, 2021
    Publication date: April 18, 2024
    Inventors: Koichi ARISAWA, Takuya SHIMOMUGI, Takaaki TAKAHARA, Haruka MATSUO, Keisuke UEMURA
  • Patent number: 11926018
    Abstract: There is provided an apparatus for polishing, comprising a polishing table configured to support and rotate a polishing pad; a holder configured to hold an object and press the object against the polishing pad; a polishing solution supply device provided with a contact member and configured to supply a polishing solution to an opening in a bottom face of the contact member in a state that the contact member comes into contact with or is adjacent to the polishing pad, thereby spreading the polishing solution on the polishing pad, the polishing solution supply device causing at least part of used polishing solution returned by rotation of the polishing pad to be dammed up by the contact member and setting the contact member either in a direction of keeping the dammed up polishing solution on the polishing pad or in a direction of discharging the dammed up polishing solution, according to an angle of the polishing solution supply device with respect to a radial direction of the polishing pad; an arm linked with
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 12, 2024
    Assignee: EBARA CORPORATION
    Inventors: Masayoshi Ito, Hisanori Matsuo, Itsuki Kobata, Takuya Moriura
  • Patent number: 11919325
    Abstract: An enclosing-sealing apparatus includes a flap opener that opens a flap of an envelope while the envelope is conveyed to an enclosing position. A first envelope detector is disposed upstream from the flap opener in an envelope conveyance direction and detects both ends of the envelope in the envelope conveyance direction. A second envelope detector is disposed downstream from the flap opener in the envelope conveyance direction and detects both ends of the envelope in the envelope conveyance direction in an open state in which the flap opens. A controller determines the open state of the flap based on a first detection result sent from the first envelope detector and a second detection result sent from the second envelope detector. The controller performs troubleshooting for enclosing the enclosure into the envelope if the controller determines that the open state of the flap is faulty.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Ricoh Company, Ltd.
    Inventors: Akira Kunieda, Michitaka Suzuki, Shinji Asami, Nobuyoshi Suzuki, Yuusuke Shibasaki, Takahiro Matsuda, Makoto Hidaka, Kazuyoshi Matsuo, Shingo Yoshizawa, Takahiro Watanabe, Takuya Morinaga
  • Publication number: 20220415990
    Abstract: A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.
    Type: Application
    Filed: September 8, 2022
    Publication date: December 29, 2022
    Inventors: MASATOMO HONJO, HIROSHI MATSUKIZONO, TAKUYA MATSUO
  • Patent number: 11476314
    Abstract: A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 18, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masatomo Honjo, Hiroshi Matsukizono, Takuya Matsuo
  • Patent number: 11411575
    Abstract: According to an embodiment, an information processing apparatus includes a computing unit and a compressing unit. The computing unit is configured to execute computation of an input layer, a hidden layer, and an output layer of a neural network. The compressing unit is configured to irreversibly compress output data of at least a part of the input layer, the hidden layer, and the output layer and output the compressed data.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: August 9, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Matsuo, Wataru Asano
  • Publication number: 20210275499
    Abstract: The invention relates to heterocyclic sulfonamide derivatives and their use in the treatment and prophylaxis of autoimmune, inflammatory, cardiovascular, neuronal, auditory, renal and metabolic mediated diseases, and to compositions containing said derivatives and processes for their preparation.
    Type: Application
    Filed: July 5, 2019
    Publication date: September 9, 2021
    Applicant: METRION BIOSCIENCES LIMITED
    Inventors: Marc ROGERS, Robert KIRBY, Gakujun SHOMI, Takuya MATSUO, Satoru KOBAYASHI, Junichiro KANAZAWA, Nobutaka YAMAOKA, Makoto TORIZUKA, Koichi SUZAWA
  • Patent number: 11018361
    Abstract: To provide a fuel cell stack device that is applicable to miniaturization of the device and does not require a pipe for discharging off-gas up to a combustion section. A fuel cell stack device including: a first manifold 2a for supplying fuel gas supplied from a reformer 12 to a plurality of fuel cells provided in a first cell stack from above, the first manifold being connected to upper ends of the plurality of fuel cells provided in the first cell stack 10a; and a second manifold 2b for recovering fuel gas discharged from the first cell stack, and supplying the recovered fuel gas to the plurality of fuel cells provided in the second cell stack from below, the second manifold being connected to lower ends of the plurality of fuel cells provided in the second cell stack 10b.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 25, 2021
    Assignee: MORIMURA SOFC TECHNOLOGY CO., LTD.
    Inventors: Naoki Watanabe, Toshiharu Otsuka, Akira Kawakami, Fumio Tsuboi, Takuya Matsuo, Takuya Hoshiko, Shuhei Tanaka
  • Patent number: 10981877
    Abstract: A production method of a compound represented by the formula [I]: or a pharmaceutically acceptable salt thereof, or a hydrate thereof.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: April 20, 2021
    Assignee: JAPAN TOBACCO INC.
    Inventors: Takahisa Motomura, Masafumi Inoue, Hirotsugu Ito, Takuya Matsuo, Koichi Suzawa, Hiroshi Yamamoto, Tsubasa Takeichi, Yasuyuki Kajimoto, Takashi Inaba, Takao Ito, Takahiro Yamasaki, Yukishige Ikemoto
  • Publication number: 20210013282
    Abstract: A display device according to the disclosure includes a substrate, a first transistor provided on the substrate, and a second transistor provided on the substrate, not overlapping the first transistor. The first transistor includes a polycrystalline silicon layer provided on the substrate, a first insulating film provided on the polycrystalline silicon layer, a first gate electrode provided on the first insulating film, and a second insulating film provided on the first gate electrode. The second transistor includes an oxide semiconductor layer provided on the first insulating film, a third insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the third insulating film. The first and third insulating films are SiOx films. The second insulating film is an SiNx film including hydrogen, and is provided overlapping the polycrystalline silicon layer, and is provided not overlapping the oxide semiconductor layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: January 14, 2021
    Inventors: MASATOMO HONJO, HIROSHI MATSUKIZONO, TAKUYA MATSUO
  • Patent number: 10686468
    Abstract: A data processing apparatus for compressing physical address values correlated to logical address values includes a first prediction unit that calculates a first predicted address value for a first input address value in input data to be compressed, a determination unit that selects an encoding processing for the first input address value according to the first predicted address value, and a compression unit configured to encode the first input address value according to the encoding processing selected by the determination unit.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 16, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuya Matsuo, Atsushi Matsumura
  • Publication number: 20190375717
    Abstract: A production method of a compound represented by the formula [I]: or a pharmaceutically acceptable salt thereof, or a hydrate thereof.
    Type: Application
    Filed: July 28, 2017
    Publication date: December 12, 2019
    Inventors: Takahisa Motomura, Masafumi Inoue, Hirotsugu Ito, Takuya Matsuo, Koichi Suzawa, Hiroshi Yamamoto, Tsubasa Takeichi, Yasuyuki Kajimoto, Takashi Inaba, Takao Ito, Takahiro Yamasaki, Yukishige Ikemoto
  • Patent number: 10505212
    Abstract: A solid oxide fuel cell apparatus 1 has: multiple fuel cell units 16; a module case 8 housing multiple fuel cell units; a heat insulating material 7 disposed to cover the area around the module case 8; a reformer 20 for reforming raw fuel gas using steam, thereby producing fuel gas; a combustion chamber 18 for combusting residual fuel gas and heating the reformer 20; a heat exchanger 23 for exchanging heat between oxidant gas and exhaust gas; and a steam generator 25, disposed within the heat insulating material 7 and on the outside of the module case 8, for exchanging heat between exhaust gas and water immediately after heat is exchanged in the heat exchanger 23, thereby producing steam.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 10, 2019
    Assignee: TOTO LTD.
    Inventors: Yousuke Akagi, Fumio Tsuboi, Takeshi Saito, Takuya Matsuo
  • Patent number: 10360101
    Abstract: According to one embodiment, a memory controller includes one or more processors configured to function as a writing unit and a reading unit. The writing unit writes data as threshold voltages of individual memory cells. The reading unit reads the written data by detecting threshold voltages of the individual memory cells. The reading unit includes a selecting unit, a detecting unit, and an estimating unit. The selecting unit selects a read-target memory cell. The detecting unit detects a first threshold voltage at a time of reading of the read-target memory cell, and a second threshold voltage at a time of reading of at least one of adjacent memory cells that are adjacent to the read-target memory cell. The estimating unit estimates a third threshold voltage as a threshold voltage at a time of writing in the read-target memory cell based on the first threshold voltage and the second threshold voltage.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoya Kodama, Takayuki Itoh, Atsushi Matsumura, Takuya Matsuo
  • Patent number: 10355297
    Abstract: A solid oxide fuel cell apparatus 1 has: multiple fuel cell units 16; a module case 8 housing multiple fuel cell units; a heat insulating material 7 disposed to cover the area around the module case 8; a reformer 20 for reforming raw fuel gas using steam, thereby producing fuel gas; a combustion chamber 18 for combusting residual fuel gas and heating the reformer 20; a heat exchanger 23 for exchanging heat between oxidant gas and exhaust gas; and a steam generator 25, disposed within the heat insulating material 7 and on the outside of the module case 8, for exchanging heat between exhaust gas and water immediately after heat is exchanged in the heat exchanger 23, thereby producing steam.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: July 16, 2019
    Assignee: TOTO LTD.
    Inventors: Yousuke Akagi, Fumio Tsuboi, Takeshi Saito, Takuya Matsuo
  • Publication number: 20190181881
    Abstract: A data processing apparatus for compressing physical address values correlated to logical address values includes a first prediction unit that calculates a first predicted address value for a first input address value in input data to be compressed, a determination unit that selects an encoding processing for the first input address value according to the first predicted address value, and a compression unit configured to encode the first input address value according to the encoding processing selected by the determination unit.
    Type: Application
    Filed: August 28, 2018
    Publication date: June 13, 2019
    Inventors: Takuya MATSUO, Atsushi MATSUMURA
  • Patent number: 10306247
    Abstract: According to an embodiment, an image decoding apparatus includes a memory, a decoder and a first filter. The memory stores reference pixels based on pixels included in a decoded pixel block. The decoder decodes encoded data in units of pixel blocks using the reference pixels to generate a first decoded pixel block, the first decoded pixel block being adjacent to the reference pixels. The first filter performs a first filtering on only the first decoded pixel block using the first decoded pixel block and part of the reference pixels perpendicularly adjacent to the first decoded pixel block in a scan direction of image decoding processing.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 28, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuya Matsuo, Takayuki Itoh, Takashi Watanabe, Atsushi Matsumura, Tomoya Kodama