Patents by Inventor Takuya MIZUTANI

Takuya MIZUTANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220293418
    Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a rotor, a nozzle, a first electrode, and a second electrode. The rotor is configured to hold a substrate and to rotate the substrate. The substrate has an outer-periphery portion and a circumferential edge. The circumferential edge is located outside the outer-periphery portion. The nozzle is configured to supply a resist liquid to the outer-periphery portion of the substrate. The first electrode is configured to receive a voltage that applies an electric charge to the resist liquid ejected from the nozzle. The second electrode is disposed at a position different from that of the first electrode. The second electrode is configured to receive a voltage that causes a Coulomb force to act on the resist liquid.
    Type: Application
    Filed: September 10, 2021
    Publication date: September 15, 2022
    Applicant: Kioxia Corporation
    Inventors: Takuya MIZUTANI, Nobuhiro KOMINE
  • Patent number: 10386736
    Abstract: According to one embodiment, an exposure apparatus performs exposure to transcribe a circuit pattern onto each of a plurality of sections on a wafer. The exposure apparatus includes a measurement device and a control device. The control device sets, on each of a first section and a second section adjacent to each other among the plurality of sections, a measurement point at a position offset from a reference position of each section. The control device causes the measurement device to measure surface information at each measurement point. The control device executes focus leveling control for exposure on the basis of the surface information measured at each measurement point.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 20, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Takuya Mizutani
  • Publication number: 20190079421
    Abstract: According to one embodiment, an exposure apparatus performs exposure to transcribe a circuit pattern onto each of a plurality of sections on a wafer. The exposure apparatus includes a measurement device and a control device. The control device sets, on each of a first section and a second section adjacent to each other among the plurality of sections, a measurement point at a position offset from a reference position of each section. The control device causes the measurement device to measure surface information at each measurement point. The control device executes focus leveling control for exposure on the basis of the surface information measured at each measurement point.
    Type: Application
    Filed: February 28, 2018
    Publication date: March 14, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Takuya MIZUTANI
  • Patent number: 9633945
    Abstract: According to one embodiment, there is provided a semiconductor device, which includes an electrode lead-out part, a planarization film, contacts, and first and second columnar patterns. The electrode lead-out part is arranged such that an electrode film and an insulating film are alternately stacked in a plurality of layers, and layers of the electrode film are arranged stepwise. The planarization film is arranged above the electrode lead-out part. The first columnar pattern extends from a lowermost portion of the electrode lead-out part to a position lower than the upper side of the planarization film by a first depth. The second columnar pattern extends from a lowermost portion of the electrode lead-out part to a position lower than the upper side of the planarization film by a second depth larger than the first depth.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: April 25, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takuya Mizutani
  • Patent number: 9548315
    Abstract: A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: January 17, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Megumi Ishiduki, Murato Kawai, Tadashi Iguchi, Yoshihiro Yanai, Takuya Inatsuka, Yoichi Minemura, Takuya Mizutani
  • Publication number: 20160315094
    Abstract: A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.
    Type: Application
    Filed: September 10, 2015
    Publication date: October 27, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Megumi ISHIDUKI, Murato KAWAI, Tadashi IGUCHI, Yoshihiro YANAI, Takuya INATSUKA, Yoichi MINEMURA, Takuya MIZUTANI
  • Publication number: 20150357410
    Abstract: According to one embodiment, it includes an object film and an opening that is formed in the object film and in which a second taper adjoining a first taper is provided. A step is provided at the boundary between the first taper and the second taper.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takuya MIZUTANI, Yuji SETTA, Kentaro MATSUNAGA