Patents by Inventor Takuya Nakajo
Takuya Nakajo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9177833Abstract: Conventional surface roughening plating technology cannot always improve the adhesion between a leadframe and a plating film and it depends on the material used for surface roughening plating. Conventional surface roughening technology by etching can only be used for leadframes made of limited materials. Improved adhesion cannot therefore be achieved between a metal member such as leadframe and a sealing resin. A manufacturing method of a semiconductor device according to one embodiment is to carry out resin sealing using a metal member such as leadframe which has been subjected to alloying treatment of a base material and Zn plated on the surface thereof.Type: GrantFiled: February 15, 2013Date of Patent: November 3, 2015Assignee: Renesas Electronics CorporationInventors: Takuya Nakajo, Masaki Tamura, Yasushi Takahashi, Keiichi Okawa, Ryoichi Kajiwara, Sigehisa Motowaki, Hiroshi Hozouji
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Publication number: 20140264383Abstract: A semiconductor device includes a die pad, an SiC chip mounted on the die pad, a porous first sintered Ag layer bonding the die pad and the SiC chip, and a reinforcing resin portion covering a surface of the first sintered Ag layer and formed in a fillet shape. The semiconductor device further includes a source lead electrically connected to a source electrode of the SiC chip, a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body which covers the SiC chip, the first sintered Ag layer, and a part of the die pad, and the reinforcing resin portion covers a part of a side surface of the SiC chip.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryoichi KAJIWARA, Takuya NAKAJO, Katsuo ARAI, Yuichi YATO, Hiroi OKA, Hiroshi HOZOJI
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Patent number: 8643185Abstract: A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 ?m to 200 ?m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.Type: GrantFiled: October 7, 2008Date of Patent: February 4, 2014Assignee: Renesas Electronics CorporationInventors: Ryoichi Kajiwara, Kazutoshi Itou, Hiroi Oka, Takuya Nakajo, Yuichi Yato
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Publication number: 20130228907Abstract: Conventional surface roughening plating technology cannot always improve the adhesion between a leadframe and a plating film and it depends on the material used for surface roughening plating. Conventional surface roughening technology by etching can only be used for leadframes made of limited materials. Improved adhesion cannot therefore be achieved between a metal member such as leadframe and a sealing resin. A manufacturing method of a semiconductor device according to one embodiment is to carry out resin sealing using a metal member such as leadframe which has been subjected to alloying treatment of a base material and Zn plated on the surface thereof.Type: ApplicationFiled: February 15, 2013Publication date: September 5, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takuya NAKAJO, Masaki TAMURA, Yasushi TAKAHASHI, Keiichi OKAWA, Ryoichi KAJIWARA, Sigehisa MOTOWAKI, Hiroshi HOZOUJI
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Patent number: 8492202Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.Type: GrantFiled: November 15, 2012Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
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Patent number: 8314484Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.Type: GrantFiled: January 21, 2010Date of Patent: November 20, 2012Assignee: Renesas Electronics CorporationInventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
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Patent number: 8252632Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).Type: GrantFiled: June 8, 2011Date of Patent: August 28, 2012Assignee: Renesas Electronics CorporationInventors: Yuichi Yato, Takuya Nakajo, Hiroi Oka
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Publication number: 20110237031Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).Type: ApplicationFiled: June 8, 2011Publication date: September 29, 2011Inventors: Yuichi YATO, Takuya NAKAJO, Hiroi OKA
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Patent number: 7977775Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).Type: GrantFiled: January 27, 2009Date of Patent: July 12, 2011Assignee: Renesas Electronics CorporationInventors: Yuichi Yato, Takuya Nakajo, Hiroi Oka
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Publication number: 20100187678Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.Type: ApplicationFiled: January 21, 2010Publication date: July 29, 2010Applicant: Renesas Technology Corp.Inventors: Ryoichi KAJIWARA, Shigehisa MOTOWAKI, Kazutoshi ITO, Toshiaki ISHII, Katsuo ARAI, Takuya NAKAJO, Hidemasa KAGII
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Publication number: 20090189264Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).Type: ApplicationFiled: January 27, 2009Publication date: July 30, 2009Inventors: Yuichi Yato, Takuya Nakajo, Hiroi Oka
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Publication number: 20090096100Abstract: A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 ?m to 200 ?m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.Type: ApplicationFiled: October 7, 2008Publication date: April 16, 2009Inventors: Ryoichi KAJIWARA, Kazutoshi Itou, Hiroi Oka, Takuya Nakajo, Yuichi Yato
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Publication number: 20080268577Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.Type: ApplicationFiled: June 30, 2008Publication date: October 30, 2008Inventors: Hidemasa KAGII, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
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Publication number: 20080220568Abstract: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion.Type: ApplicationFiled: May 8, 2008Publication date: September 11, 2008Inventors: Akira MUTO, Ichio Shimizu, Katsuo Arai, Hidemasa Kagii, Hiroshi Sato, Hiroyuki Nakamura, Takuya Nakajo, Keiichi Okawa, Masahiko Osaka
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Patent number: 7405469Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.Type: GrantFiled: April 13, 2007Date of Patent: July 29, 2008Assignee: Renesas Technology Corp.Inventors: Hidemasa Kagii, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
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Patent number: 7374965Abstract: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion.Type: GrantFiled: February 7, 2006Date of Patent: May 20, 2008Assignee: Renesas Technology Corp.Inventors: Akira Muto, Ichio Shimizu, Katsuo Arai, Hidemasa Kagii, Hiroshi Sato, Hiroyuki Nakamura, Takuya Nakajo, Keiichi Okawa, Masahiko Osaka
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Publication number: 20070210430Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.Type: ApplicationFiled: April 13, 2007Publication date: September 13, 2007Inventors: Hidemasa Kagii, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
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Patent number: 7220617Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.Type: GrantFiled: February 8, 2006Date of Patent: May 22, 2007Assignee: Renesas Technology, Corp.Inventors: Hidemasa Kagii, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
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Publication number: 20060177967Abstract: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion.Type: ApplicationFiled: February 7, 2006Publication date: August 10, 2006Inventors: Akira Muto, Ichio Shimizu, Katsuo Arai, Hidemasa Kagii, Hiroshi Sato, Hiroyuki Nakamura, Takuya Nakajo, Keiichi Okawa, Masahiko Osaka
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Publication number: 20060175700Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.Type: ApplicationFiled: February 8, 2006Publication date: August 10, 2006Inventors: Hidemasa Kagii, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka