Abstract: A multi-path voltage-controlled oscillator (VCO) includes a VCO core circuit and a control voltage generator circuit. The VCO core circuit includes a varactor that has a control node for receiving a control voltage. The control voltage generator circuit receives at least one proportional path (P-path) control input and an integral path (I-path) control input, and generates and outputs the control voltage to the control node of the varactor according to the at least one P-path control input and the I-path control input.

Abstract: A line receiver is described. The line receiver may be configured to receive signals transmitted via a communication channel, such as a metal trace on a printed circuit board or a cable. The receiver may comprise a buffer and circuitry for enhancing the trans-conductance gain of the buffer. By enhancing the trans-conductance gain of the buffer, linearity may be improved and susceptibility to process and temperature variations may be limited. Enhancement of the trans-conductance gain may be performed using feedback circuitry coupled to the buffer. The receiver may further comprise mirror circuitry configured to provide a desired current to the load. The receiver may further comprise a gain stage for setting the gain of the receiver to a desired level.

Abstract: A line receiver including an analog-to-digital converter is described. The line receiver may include an input stage, a first sampling stage, an integration stage, and a second sampling stage. The input stage may be configured to receive an input voltage representative of a signal transmitted by a transmitter, and to convert the input voltage to a current. The input stage may include a trans-conductance stage. The current may be sampled using the first sampling stage. The sampled current may be converted to a voltage using the integration stage. The integration stage may include a trans-impedance stage. The voltage obtained using the integration stage may be sampled using the second sampling stage.

Abstract: A line driver for signal equalization is described. The line driver may comprise an equalization driver and a gating circuit. The gating circuit may be configured to gate the equalization driver between a first transition and a second transition, such as between a rising edge and a falling edge. The gating circuit may comprise one or more delay elements, such as one or more inverters, configured to generate the second transition in response to receiving the first transition, where the second transition is delayed with respect to the first transition. Such line driver may be used to signals having high data rates to transmission lines, such as cables or metal connection on printed circuit boards.

Abstract: A line receiver including an analog-to-digital converter is described. The line receiver may include an input stage, a first sampling stage, an integration stage, and a second sampling stage. The input stage may be configured to receive an input voltage representative of a signal transmitted by a transmitter, and to convert the input voltage to a current. The input stage may include a trans-conductance stage. The current may be sampled using the first sampling stage. The sampled current may be converted to a voltage using the integration stage. The integration stage may include a trans-impedance stage. The voltage obtained using the integration stage may be sampled using the second sampling stage.

Abstract: A line receiver is described. The line receiver may be configured to receive signals transmitted via a communication channel, such as a metal trace on a printed circuit board or a cable. The receiver may comprise a buffer and circuitry for enhancing the trans-conductance gain of the buffer. By enhancing the trans-conductance gain of the buffer, linearity may be improved and susceptibility to process and temperature variations may be limited. Enhancement of the trans-conductance gain may be performed using feedback circuitry coupled to the buffer. The receiver may further comprise mirror circuitry configured to provide a desired current to the load. The receiver may further comprise a gain stage for setting the gain of the receiver to a desired level.

Abstract: A driver circuit for driving a transmission line, such as a cable or a metal trace on a printed circuit board is described. The driver may be configured to drive lines with voltages exceeding the maximum voltage than a transistor can withstand for a given fabrication node. The driver may be configured to receive a supply voltage larger than that indicated by manufacturers. The driver may use a fast path and a slow path. Signals provided by the slow path and the fast path may be combine to adapt the input signals to levels that do cause stress to a transistor. A plurality of drivers of the type described herein may be used to provide digital-to-analog conversion.

Abstract: A line driver for signal equalization is described. The line driver may comprise an equalization driver and a gating circuit. The gating circuit may be configured to gate the equalization driver between a first transition and a second transition, such as between a rising edge and a falling edge. The gating circuit may comprise one or more delay elements, such as one or more inverters, configured to generate the second transition in response to receiving the first transition, where the second transition is delayed with respect to the first transition. Such line driver may be used to signals having high data rates to transmission lines, such as cables or metal connection on printed circuit boards.

Abstract: A driver circuit for driving a transmission line, such as a cable or a metal trace on a printed circuit board is described. The driver may be configured to drive lines with voltages exceeding the maximum voltage than a transistor can withstand for a given fabrication node. The driver may be configured to receive a supply voltage larger than that indicated by manufacturers. The driver may use a fast path and a slow path. Signals provided by the slow path and the fast path may be combine to adapt the input signals to levels that do cause stress to a transistor. A plurality of drivers of the type described herein may be used to provide digital-to-analog conversion.

Abstract: A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

Abstract: A multi-lane analog to digital converter (ADC) samples an analog input according to multiple phases of a sampling clock. Ideally, the multiple phases of the sampling clock are non-overlapping. The multi-lane ADC includes one or more reset switches to remove any residual samples that can remain after their conversion from an analog signal domain to a digital signal domain. As a result of this removal, the multiple phases of the sampling clock need not to ideally coincide with one other. Rather, some overlap between the multiple phases of the sampling clock can exist while having digital output samples still accurately represent the analog input.

Abstract: A device includes process mitigating timing (PMT) circuitry. The PMT circuitry allows for adjustment of a clock signal while compensating for process variation within the PMT circuitry. The PMT circuitry may include process mitigating buffer (PMB) circuitry. The PMB circuitry may utilize replica circuitry and a calibrated resistance to generate a calibrated bias voltage. The calibrated bias voltage may be used to drive component buffer circuits to create a calibrated current response. The calibrated current response may correspond to a selected output impedance for the component buffer circuits. The select output impedance may be used in concert with a variable capacitance to adjust a clock signal in manner that is independent of the process variation within the PMT circuitry.

Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Abstract: A device includes process mitigating timing (PMT) circuitry. The PMT circuitry allows for adjustment of a clock signal while compensating for process variation within the PMT circuitry. The PMT circuitry may include process mitigating buffer (PMB) circuitry. The PMB circuitry may utilize replica circuitry and a calibrated resistance to generate a calibrated bias voltage. The calibrated bias voltage may be used to drive component buffer circuits to create a calibrated current response. The calibrated current response may correspond to a selected output impedance for the component buffer circuits. The select output impedance may be used in concert with a variable capacitance to adjust a clock signal in manner that is independent of the process variation within the PMT circuitry.

Abstract: Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.

Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch that includes a first driver coupled in series with an equalization capacitor, and a second branch that includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch, and the first branch may be configurable to enable one of passive equalization or slew-rate control of the signal based on a mode control signal.

Abstract: A transmission line driver including an output configured to have a load impedance is provided. The transmission line driver includes a pull-up circuit coupled in series with the output. The transmission line driver also includes a pull-down circuit coupled in series with the output. The transmission line driver includes a shunt circuit having an adjustable impedance. The shunt circuit is coupled in parallel to the output. The shunt circuit is coupled to the pull-up circuit and the pull-down circuit. The shunt circuit is configured to receive a shunt control signal to adjust the adjustable impedance to provide linear control of an output swing at the output.