Patents by Inventor Tamio Miyamura

Tamio Miyamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5754061
    Abstract: A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: May 19, 1998
    Assignee: Fujitsu Limited
    Inventors: Shinzou Satou, Kou Ebihara, Akiyoshi Suzuki, Keisuke Ishiwata, Kouji Miki, Hitoshi Ohmichi, Tamio Miyamura, Masamichi Kamiyama
  • Patent number: 4694431
    Abstract: A semiconductor memory device having a PROM with an output register has an initialize input terminal and a programmable initial data memory cell for each bit. When an initialize input signal is supplied to the initialize input terminal, the output register is cleared or present in accordance with the content of the initial data memory cell, whereby the reduction of adaptability caused by a decrease in input terminals can be prevented, a circuit arrangement can be simplified, and a high degree of integration and high-speed operation can be achieved.
    Type: Grant
    Filed: September 23, 1985
    Date of Patent: September 15, 1987
    Assignee: Fujitsu Limited
    Inventors: Tamio Miyamura, Takashi Ohkawa
  • Patent number: 4599688
    Abstract: A semiconductor memory device includes control circuits which are at least a switching circuit and program circuits provided with a constant current source. The switching circuit is mainly comprised of an input side transistor and an output side transistor in the form of a thyristor, and both transistors are on only when a write operation is conducted by the program circuits and the constant current source. If no write operation is conducted, these transistors are both off.
    Type: Grant
    Filed: June 28, 1983
    Date of Patent: July 8, 1986
    Assignee: Fujitsu Limited
    Inventors: Kouji Ueno, Tamio Miyamura
  • Patent number: 4488261
    Abstract: A field programmable device comprises a plurality of word lines, a plurality of bit lines which are disposed in a manner to intersect the word lines, a plurality of cells which are respectively connected to the word lines and the bit lines, and a plurality voltage supply means, each of comprising a series connection of a resistor and a diode whose cathode is connected to each of the word lines. The voltage supply means supplies non-selected the word lines with a voltage high enough to prevent parasitic P-N-P-N elements, which are formed by the cells and the word lines, from turning on. Thus a programming current is hindered from flowing out of the cells.
    Type: Grant
    Filed: March 1, 1982
    Date of Patent: December 11, 1984
    Assignee: Fujitsu Limited
    Inventors: Kouji Ueno, Tamio Miyamura
  • Patent number: 4424582
    Abstract: A semiconductor memory device which writes information by rendering particular memory cells conductive or non-conductive, wherein, when a selected memory cell is to be read out, a power supply voltage is applied to the collector of a transistor which feeds a base current to a final stage transistor of a decoder circuit which is connected to word lines, and when information is to be written in, a voltage higher than the power supply voltage is applied to the same collector.
    Type: Grant
    Filed: April 21, 1980
    Date of Patent: January 3, 1984
    Assignee: Fujitsu Limited
    Inventors: Toshitaka Fukushima, Kazumi Koyama, Kouji Ueno, Tamio Miyamura, Yuichi Kawabata
  • Patent number: 4347584
    Abstract: A PROM device having the improved bit address decoders composed of a plurality of AND gates, each of the AND gates comprising PNP type transistors, to each base of which is applied an address signal from the bit address inverters. Each collector of these transistors is connected to ground, and each emitter is connected to the output terminal of the bit address decoder.
    Type: Grant
    Filed: April 21, 1980
    Date of Patent: August 31, 1982
    Assignee: Fujitsu Limited
    Inventors: Toshitaka Fukushima, Kazumi Koyama, Kouji Ueno, Yuichi Kawabata, Tamio Miyamura
  • Patent number: 4319341
    Abstract: A program circuit for permanently storing data into a programmable read only memory. A programming current (received from an external source) is connected to the selected bit line through a Darlington pair which is controlled by the bit decoding circuitry. Thus, the bit decoding circuitry is not required to pass the large programming current, and the programming current is not significantly shunted away from the selected bit line. To facilitate use of the Darlington configuration, a constant current source is provided for each bit line within a set of bit lines. The program circuit includes at least one switching means for connecting the program current to a selected bit line, a bit decoder connected to the control inputs of the switching means for selecting a bit line in response to the addressing signals input to the bit decoder and a control current supplying means for supplying a control current to the control inputs of the switching means.
    Type: Grant
    Filed: April 21, 1980
    Date of Patent: March 9, 1982
    Assignee: Fujitsu Limited
    Inventors: Toshitaka Fukushima, Kazumi Koyama, Kouji Ueno, Tamio Miyamura, Yuichi Kawabata
  • Patent number: 4319300
    Abstract: A screw-in station protector assembly includes a carrier housing containing a shorting cage which is biased by a compression to urge the cage and gas tube arrester assembly outwardly. The gas tube assembly contained within the cage includes a two electrode gas tube. The gas tube is within a jacket which forms a sealed external back-up air gap protector. The screw-in-assembly is particularly adapted for retro-fitting/replacement of carbon block arresters without modification.
    Type: Grant
    Filed: November 13, 1979
    Date of Patent: March 9, 1982
    Assignees: TII Industries, Inc., Fujitsu Limited
    Inventors: John Napiorkowski, Raymond D. Jones, Toshitaka Fukushima, Kazumi Koyama, Kouji Ueno, Tamio Miyamura, Yuichi Kawabata