Abstract: In one embodiment, an in-network compute resource assignment system includes a network device to receive a request to select resources to perform a processing job, wherein the request includes at least one resource requirement of the processing job, and end point devices assigned to perform the processing job, a memory to store a state of in-network compute-resources indicating resource usage of the in-network compute-resources by other processing jobs, and a processor to manage the stored state, and responsively to receiving the request, selecting ones of the in-network compute-resources to perform the processing job based on: (a) a network topology of a network including the in-network compute-resources; (b) the state of the in-network compute-resources; and (c) the at least one resource requirement of the processing job.

Abstract: A method for communication includes partitioning local links in a subnetwork of a packet data network into at least first and second groups. For each local link that connects a first upper-tier switch to a first lower-tier switch in the subnetwork, a corresponding detour route is defined, passing through a first local link belonging to the first group from the first upper-tier switch to a second lower-tier switch, and from the second lower-tier switch over a second local link to a second upper-tier switch, and from the second upper-tier switch over a third local link belonging to the second group to the first lower-tier switch. Upon a failure of the local link connecting the first upper-tier switch to the first lower-tier switch, data packets arriving from the network at the first upper-tier switch are rerouted to pass via the corresponding detour route to the first lower-tier switch.

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.

Abstract: A method for communication includes partitioning local links in a subnetwork of a packet data network into at least first and second groups. For each local link that connects a first upper-tier switch to a first lower-tier switch in the subnetwork, a corresponding detour route is defined, passing through a first local link belonging to the first group from the first upper-tier switch to a second lower-tier switch, and from the second lower-tier switch over a second local link to a second upper-tier switch, and from the second upper-tier switch over a third local link belonging to the second group to the first lower-tier switch. Upon a failure of the local link connecting the first upper-tier switch to the first lower-tier switch, data packets arriving from the network at the first upper-tier switch are rerouted to pass via the corresponding detour route to the first lower-tier switch.

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

Abstract: A communication network includes multiple nodes, which are arranged in groups such that the nodes in each group are interconnected in a bipartite topology and the groups are interconnected in a mesh topology. The nodes are configured to convey traffic between source hosts and respective destination hosts by routing packets among the nodes on paths that do not traverse any intermediate hosts other than the source and destination hosts.

Abstract: A communication network includes multiple nodes, which are arranged in groups such that the nodes in each group are interconnected in a bipartite topology and the groups are interconnected in a mesh topology. The nodes are configured to convey traffic between source hosts and respective destination hosts by routing packets among the nodes on paths that do not traverse any intermediate hosts other than the source and destination hosts.