Patents by Inventor Tammo Spalink

Tammo Spalink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11652484
    Abstract: An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding sub array of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: May 16, 2023
    Assignee: Google LLC
    Inventors: Michial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
  • Publication number: 20230010315
    Abstract: A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 12, 2023
    Inventors: Michial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
  • Patent number: 11451229
    Abstract: A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 20, 2022
    Assignee: Google LLC
    Inventors: Michial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
  • Patent number: 11088694
    Abstract: An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 10, 2021
    Assignee: X Development LLC
    Inventors: Michial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
  • Patent number: 10879904
    Abstract: A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 29, 2020
    Assignee: X Development LLC
    Inventors: Michial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
  • Patent number: 10790828
    Abstract: An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: September 29, 2020
    Assignee: X Development LLC
    Inventors: Michial Allen Gunter, Charles Henry Leichner, IV, Tammo Spalink
  • Patent number: 10453551
    Abstract: The behavior and/or internal activities of a microorganism can be simulated using a model of the microorganism. Such simulations can be used to determine the efficacy of treatments, disinfectants, antibiotics, chemotherapies, or other methods of interacting with the microorganism, or to provide some other information about the microorganism. Systems and methods are provided herein for fitting, refining, or otherwise improving such models in an automated fashion. Such systems and methods include performing whole-cell experiments to determine a correspondence between the predictions of such models and the actual behavior of samples of the microorganism. Such systems and methods also include, based on such determined correspondences, directly assessing determined discrete sets of properties of the microorganism and/or of constituents of the microorganism and updating parameters of the model corresponding to the properties of the discrete set such that the overall accuracy of the model is improved.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: October 22, 2019
    Assignee: X Development LLC
    Inventors: Chirath Thouppaurachchi, Ian Peikon, Jason Thompson, Tammo Spalink
  • Publication number: 20170357748
    Abstract: The behavior and/or internal activities of a microorganism can be simulated using a model of the microorganism. Such simulations can be used to determine the efficacy of treatments, disinfectants, antibiotics, chemotherapies, or other methods of interacting with the microorganism, or to provide some other information about the microorganism. Systems and methods are provided herein for fitting, refining, or otherwise improving such models in an automated fashion. Such systems and methods include performing whole-cell experiments to determine a correspondence between the predictions of such models and the actual behavior of samples of the microorganism. Such systems and methods also include, based on such determined correspondences, directly assessing determined discrete sets of properties of the microorganism and/or of constituents of the microorganism and updating parameters of the model corresponding to the properties of the discrete set such that the overall accuracy of the model is improved.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 14, 2017
    Inventors: Chirath Thouppaurachchi, Ian Peikon, Jason Thompson, Tammo Spalink
  • Patent number: 8523073
    Abstract: A system and method is disclosed for automatically providing information to a newly-manufactured computing device. During the manufacture of a new computing device at an assembly line, a camera integrated with the computing device is automatically activated as a barcode scanner. On the camera viewing a barcode that includes device-specific configuration information, the barcode is read by the computing device to read the device-specific configuration information for storage in a non-volatile memory of the device.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: September 3, 2013
    Assignee: Google Inc.
    Inventors: Wai Hong Tam, Tammo Spalink
  • Publication number: 20130082098
    Abstract: A system and method is disclosed for automatically providing information to a newly-manufactured computing device. During the manufacture of a new computing device at an assembly line, a camera integrated with the computing device is automatically activated as a barcode scanner. On the camera viewing a barcode that includes device-specific configuration information, the barcode is read by the computing device to read the device-specific configuration information for storage in a non-volatile memory of the device.
    Type: Application
    Filed: July 16, 2012
    Publication date: April 4, 2013
    Applicant: GOOGLE INC.
    Inventors: Wai Hong TAM, Tammo SPALINK
  • Patent number: 8245934
    Abstract: A system and method is disclosed for automatically providing information to a newly-manufactured computing device. During the manufacture of a new computing device at an assembly line, a camera integrated with the computing device is automatically activated as a barcode scanner. On the camera viewing a barcode that includes device-specific configuration information, the barcode is read by the computing device to read the device-specific configuration information for storage in a non-volatile memory of the device.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: August 21, 2012
    Assignee: Google Inc.
    Inventors: Wai Hong Tam, Tammo Spalink
  • Patent number: 8214691
    Abstract: A system and method is disclosed for testing internet functionality of a computing device in a simulated Internet environment. In a testing environment, one or more local web servers are isolated from the Internet and configured to simulate one or more websites on the Internet. A request for a website located on the Internet is received from a computing device under test at a testing station. In response to receiving the request, information which simulates the website located on the Internet is provided to the computing device by the one or more local web servers, without access to the Internet.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: July 3, 2012
    Assignee: Google Inc.
    Inventors: Tammo Spalink, Vincent Wu
  • Patent number: 8214692
    Abstract: A system and method is disclosed for enforcing a third-party factory test during a quality verification of a newly-manufactured computing device. During an assembly line quality verification, a factory implemented test and a required third-party factory test are executed on a computing device, and then the execution verified by an external process. On verifying the required third-party factory test was executed, the computing device is configured to execute a release image on a subsequent startup of the computing device.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: July 3, 2012
    Assignee: Google Inc.
    Inventors: Tammo Spalink, Hung-Te Lin, Vincent Wu