Patents by Inventor Tamotsu Wada
Tamotsu Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7323351Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: GrantFiled: July 18, 2005Date of Patent: January 29, 2008Assignee: Sharp Kabushiki KaishaInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
-
Patent number: 7279348Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: GrantFiled: July 18, 2005Date of Patent: October 9, 2007Assignee: Sharp Kabushiki KaishaInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
-
Patent number: 7161181Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: GrantFiled: July 18, 2005Date of Patent: January 9, 2007Assignee: Sharp Kabushiki KaishaInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
-
Publication number: 20050269572Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: ApplicationFiled: July 18, 2005Publication date: December 8, 2005Applicant: Sharp CorporationInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
-
Publication number: 20050255621Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: ApplicationFiled: July 18, 2005Publication date: November 17, 2005Applicant: Sharp CorporationInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
-
Publication number: 20050250264Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: ApplicationFiled: July 18, 2005Publication date: November 10, 2005Applicant: Sharp CorporationInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
-
Patent number: 6939750Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: GrantFiled: May 5, 2004Date of Patent: September 6, 2005Assignee: Fujitsu Display Technologies CorporationInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
-
Publication number: 20040232424Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: ApplicationFiled: May 5, 2004Publication date: November 25, 2004Applicant: FUJITSU DISPLAY TECHNOLOGIES CORPORATIONInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
-
Publication number: 20030151049Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.Type: ApplicationFiled: December 19, 2002Publication date: August 14, 2003Applicant: FUJITSU DISPLAY TECHNOLOGIES CORPORATIONInventors: Kazushige Hotta, Hiroyuki Yaegashi, Takuya Watanabe, Tamotsu Wada
-
Patent number: 6156662Abstract: A method of fabricating a liquid crystal display device includes the step of removing a porous anodic oxide film selectively with respect to a barrier-type anodic oxide film covering a gate electrode pattern of a thin-film transistor, wherein the step of removing the porous anodic oxide film is conducted after the step of disconnecting a bridging conductor pattern used for supplying electric current at the time of anodic oxidation process of the gate electrode.Type: GrantFiled: March 29, 1999Date of Patent: December 5, 2000Assignee: Fujitsu LimitedInventors: Tatsuya Ohori, Tamotsu Wada, Kohji Ohgata, Tatsuya Kakehi, Ken-ichi Yanai
-
Patent number: 6130456Abstract: A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode.Type: GrantFiled: October 22, 1997Date of Patent: October 10, 2000Assignee: Fujitsu LimitedInventors: Ken-ichi Oki, Ken-ichi Yanai, Tamotsu Wada, Koji Ohgata, Yutaka Takizawa, Masahiro Okabe, Tsutomu Tanaka
-
Patent number: 5994173Abstract: A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode.Type: GrantFiled: September 26, 1997Date of Patent: November 30, 1999Assignee: Fujitsu LimitedInventors: Ken-ichi Oki, Ken-ichi Yanai, Tamotsu Wada, Koji Ohgata, Yutaka Takizawa, Masahiro Okabe, Tsutomu Tanaka
-
Patent number: 5728592Abstract: A thin film transistor matrix device is fabricated by forming a transparent conductor film and a metal film on an insulating substrate in this order. The metal film and the transparent conductor film are together patterned to form picture element electrodes, and drain bus lines or gate bus lines. Source electrodes and drain electrodes may also be formed from the transparent conductor film and metal film. A semiconductor layer, an insulating film and a conductor film may be formed on the entire surface in this order. In this case, the conductor film, the insulator film and the semiconductor layer are patterned to form an active layer from the semiconductor layer, gate insulating films from the insulating film, and gate electrodes and gate bus lines from the conductor film. By patterning the conductor film, the insulating film and the semiconductor layer, the metal film of the picture element electrodes and drain bus lines is exposed.Type: GrantFiled: July 6, 1995Date of Patent: March 17, 1998Assignee: Fujitsu Ltd.Inventors: Ken-ichi Oki, Ken-ichi Yanai, Tamotsu Wada, Koji Ohgata, Yutaka Takizawa, Masahiro Okabe, Tsutomu Tanaka
-
Patent number: 5518940Abstract: A method of manufacturing a semiconductor device according to the present invention includes a process of introducing impurities into a semiconductor layer with a gate electrode and a resist film as a mask after a resist film is formed on the top and the side of the gate electrode by soaking the gate electrode on a semiconductor layer in an electrolyte containing resist and applying voltage to the gate electrode.Type: GrantFiled: January 5, 1995Date of Patent: May 21, 1996Assignee: Fujitsu LimitedInventors: Mari Hodate, Norihisa Matsumoto, Kohji Ohgata, Tamotsu Wada, Ken-iti Yanai, Ken-ichi Oki, Yasuyoshi Mishima, Michiko Takei, Tatsuya Kakehi, Masahiro Okabe