Patents by Inventor Tamotsu Yoshiki

Tamotsu Yoshiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock synchronization method
    Patent number: 9898035
    Abstract: The first synchronous FF is disposed at the starting point of the clock tree of the frequency-divided clock of each lower hierarchical block, and the first maximum delay time of the reference clock from the branch point of the reference clock and the frequency-divided clock to the first synchronous FF is acquired. The second maximum delay time of the reference clock between adjacent two of second synchronous FFs is determined so as to be less than half the period of the reference clock. The number of stages of the second synchronous FFs is determined according to the first and second maximum delay times. The target delay time from the branch point is determined so as to be not more than the second maximum delay time, and the second synchronous FF and a latch are disposed so as to achieve the target delay time.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: February 20, 2018
    Assignee: MEGACHIPS CORPORATION
    Inventor: Tamotsu Yoshiki
  • CLOCK SYNCHRONIZATION METHOD
    Publication number: 20160239042
    Abstract: The first synchronous FF is disposed at the starting point of the clock tree of the frequency-divided clock of each lower hierarchical block, and the first maximum delay time of the reference clock from the branch point of the reference clock and the frequency-divided clock to the first synchronous FF is acquired. The second maximum delay time of the reference clock between adjacent two of second synchronous FFs is determined so as to be less than half the period of the reference clock. The number of stages of the second synchronous FFs is determined according to the first and second maximum delay times. The target delay time from the branch point is determined so as to be not more than the second maximum delay time, and the second synchronous FF and a latch are disposed so as to achieve the target delay time.
    Type: Application
    Filed: February 16, 2016
    Publication date: August 18, 2016
    Applicant: MegaChips Corporation
    Inventor: Tamotsu Yoshiki