Patents by Inventor Tan F. Lei

Tan F. Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • N-INP Schottky diode structure and a method of making the same
    Patent number: 5610098
    Abstract: A new Schottky diode structure, Pt/Al/n-InP, is disclosed in the present invention. The thickness of Al layer of the Schottky diode structure is restricted in a range of about 80-120 .ANG.. This structure gives a barrier height of 0.74 eV and an ideality factor of 1.11 after it was annealed at 300.degree. C. for 10 min. This is due to the formation of Aluminum-oxide, as the interfacial layer to improve barrier height. A method of preparing this Schottky diode structure is also disclosed in the present invention.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: March 11, 1997
    Assignee: National Science Council
    Inventors: Wen C. Huang, Tan F. Lei, Chung L. Lee
  • N-InP Schottky diode structure and a method of making the same
    Patent number: 5517054
    Abstract: A new Schottky diode structure, Pt/Al/n-InP, is disclosed in the present invention. The thickness of Al layer of the Schottky diode structure is restricted in a range of about 80-120 .ANG.. This structure gives a barrier height of 0.74 eV and an ideality factor of 1.11 after it was annealed at 300.degree. C. for 10 min. This is due to the formation of Aluminum-oxide, as the interfacial layer to improve barrier height. A method of preparing this Schottky diode structure is also disclosed in the present invention.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: May 14, 1996
    Assignee: National Science Council
    Inventors: Wen C. Huang, Tan F. Lei, Chung L. Lee
  • High-density electronic head
    Patent number: 5506737
    Abstract: A VLSI-compatible process for the manufacturing of a monolithic high-density electronic head in the form of a single composite IC chip for reading and/or writing multiple tracks of magnetically recordable information. The VLSI-compatible process comprises the steps of fabricating a digital signal process circuit as well as other desired circuit components on a substrate, then fabricating a plurality of read and/or write elements on the same substrate using a thin film technique. Because the silicon-based materials, which are used to replace the conventional magneto-resistant elements, show very little magneto-resistance effect at room temperature, a magnetically sensitive layer is provided which comprises a double-drain polycrystalline thin-films transistor (DTFT) to provide the required sensitivity.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: April 9, 1996
    Assignee: Industrial Technology Research Institute
    Inventors: Hsiao-Yi Lin, Tan F. Lei, Tsung-Shin Chen