Abstract: An improved circuit for crosstalk cancellation may be used to provide improved receiver crosstalk cancelation. These solutions may include a high-pass filter that is configured to be matched to victim path. These solutions may reduce or eliminate the use of a unity gain buffer and in-line high-pass filter, which may reduce design complexity and improve performance. These solutions provide crosstalk cancellation that requires less power, is less complex, is less sensitive to temperature and voltage, and is more effective at providing crosstalk cancellation. This improved crosstalk cancellation further provides channel eye height improvement, reduced EHI temperature sensitivity, reduced EHI voltage sensitivity, reduced design complexity, and reduced silicon circuit area.

Abstract: Described herein is a phase-locked loop including a phase detector, a charge pump, a filter, and a self-biased voltage-controlled oscillator having an oscillating frequency controlled by a control signal. The self-biased voltage-controlled oscillator includes a first differentiator and a second differentiator. The second differentiator has an input node coupled to the output node of the first differentiator, and an output node coupled to the input node of the first differentiator. In one embodiment, each of the first and the second differentiators has adjustable resistance and/or capacitance, and the oscillating frequency of the voltage-controlled oscillator is independent of power supply provided to the first and the second differentiators.

Abstract: Described herein is a self-biased oscillator. The self-biased oscillator comprises a first differentiator with adjustable resistance or capacitance, the first differentiator having an output node and an input node; and a second differentiator with adjustable resistance or capacitance, the second differentiator having an input node coupled to the output node of the first differentiator, and having an output node coupled to the input node of the first differentiator.

Abstract: Described herein is a self-biased oscillator. The self-biased oscillator comprises a first differentiator with adjustable resistance or capacitance, the first differentiator having an output node and an input node; and a second differentiator with adjustable resistance or capacitance, the second differentiator having an input node coupled to the output node of the first differentiator, and having an output node coupled to the input node of the first differentiator.

Abstract: In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic tuning circuit for a continuous-time equalizer (CTE). In some embodiments, the automatic tuning circuit automatically tunes the magnitude response as a function of frequency of the CTE.

Abstract: In one embodiment, the present invention includes a receiver having two complementary input sense amplifiers to receive, amplify and latch a differential signal and to output complementary stage differential output signals to a latch coupled to receive and combine the n? them into a latched differential output signal. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic calibration circuit for a continuous-time equalizer (CTE). In some embodiments, the calibration circuit separately locks the direct (DC) voltage swing and the alternating (AC) voltage swing of a CTE to reference voltage.

Abstract: In one embodiment, a receiver includes a voltage margin controller, a set of first components coupled to the voltage margin control, and a set of offset compensation controllers coupled to the set of first components.

Abstract: A circuit to synchronize the phase of a distributed clock signal to a received clock signal. Embodiments include a control loop comprising a phase interpolator, a clock distribution network, and a data receiver. The clock distribution network provides a sampling clock signal to clock the data receiver. The data receiver receives as its input the received clock signal. Control logic maps a subset of the output samples to a value, and this value is added to the phase introduced by the phase interpolator to provide an updated phase. Embodiments include a second phase interpolator and a second distribution network to clock a second data receiver, where the second data receiver receives the data. The control logic adjusts the second phase interpolator in the same way that it adjusts the phase interpolator. The two data receivers are matched to each other, and the two clock distribution networks are matched to each other. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a receiver having two complementary input sense amplifiers to receive, amplify and latch a differential signal and to output complementary stage differential output signals to a latch coupled to receive and combine the n? them into a latched differential output signal. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic calibration circuit for a continuous-time equalizer (CTE). In some embodiments, the calibration circuit separately locks the direct (DC) voltage swing and the alternating (AC) voltage swing of a CTE to reference voltage.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic tuning circuit for a continuous-time equalizer (CTE). In some embodiments, the automatic tuning circuit automatically tunes the magnitude response as a function of frequency of the CTE.

Abstract: In some embodiments, a receiver latch circuit, includes a dynamic latch having at least one input terminal to receive an input data signal and at least one latch terminal. The dynamic latch is adapted to generate an amplified output data signal based at least in part on the input data signal. The dynamic latch includes at least one capacitor, coupled between the at least one input terminal and the at least one latch terminal, to reduce intersymbol interference in the input data signal.

Abstract: A circuit to synchronize the phase of a distributed clock signal to a received clock signal. Embodiments include a control loop comprising a phase interpolator, a clock distribution network, and a data receiver. The clock distribution network provides a sampling clock signal to clock the data receiver. The data receiver receives as its input the received clock signal. Control logic maps a subset of the output samples to a value, and this value is added to the phase introduced by the phase interpolator to provide an updated phase. Embodiments include a second phase interpolator and a second distribution network to clock a second data receiver, where the second data receiver receives the data. The control logic adjusts the second phase interpolator in the same way that it adjusts the phase interpolator. The two data receivers are matched to each other, and the two clock distribution networks are matched to each other. Other embodiments are described and claimed.

Abstract: In some embodiments, a receiver latch circuit, includes a dynamic latch having at least one input terminal to receive an input data signal and at least one latch terminal. The dynamic latch is adapted to generate an amplified output data signal based at least in part on the input data signal. The dynamic latch includes at least one capacitor, coupled between the at least one input terminal and the at least one latch terminal, to reduce intersymbol interference in the input data signal.

Abstract: In one embodiment, a receiver includes a voltage margin controller, a set of first components coupled to the voltage margin control, and a set of offset compensation controllers coupled to the set of first components.