Abstract: A method for reproducible parallel discrete-event simulation at electronic system level implemented by means of a multi-core computer system, the simulation method comprising a succession of evaluation phases, implemented by a simulation kernel executed by the computer system, comprising the following steps: parallel process scheduling; dynamic detection of shared addresses of at least one shared memory of an electronic system simulated by concurrent processes, at addresses of the shared memory, using a state machine, respectively associated with each address of the shared memory; avoidance of access conflicts at addresses of the shared memory by concurrent processes, by pre-emption of a process by the kernel when the process introduces an inter-process dependency of “read after write” or “write after read or write” type; verification of access conflicts at shared-memory addresses by analysis of the inter-process dependencies using a trace of the accesses to the shared-memory addresses of each evaluation phas

Abstract: An electronic system-level reproducible parallel discrete event simulation method implemented by way of a multicore computing system, the simulation method includes a succession of evaluation phases, implemented by a simulation kernel executed by the computing system, comprising the following steps: parallel scheduling of processes; dynamically detecting shared addresses; avoiding access conflicts to addresses of the shared memory; verifying access conflicts to shared memory addresses; rolling back, upon detecting at least one conflict; and generating an execution trace for the subsequent identical reproduction of the simulation.

Abstract: An electronic system-level parallel simulation method by means of a multi-core computer system, comprising the parallel evaluation of a plurality of concurrent processes of the simulation on a plurality of cores of the computer system and comprising a sub-method of detection of conflicts of access to a shared memory of a simulated electronic system, the sub-method being implemented by a simulation kernel executed by the computer system and comprises: a step of construction of an oriented graph representative of access to the shared memory by the processes evaluated by the concurrent processes; and a step of detection of loops in the graph; a loop being considered representative of a conflict of access to the shared memory. A computer program product for implementing such a method is provided.

Abstract: A distributed computation system comprising computation units and memory shared between computation units, comprises a hardware module for detecting conflicts of access of computation units to shared memory; each hardware module for detecting conflicts configured to: store a probabilistic data structure, indicative of the addresses of shared memory involved in the current transactions; receive at least one message indicative of request for access, by one computation unit to an address of shared memory; determine, from a probabilistic data structure, whether the address is already involved in a current transaction, and transmit a message indicating presence or absence of access conflicts; receive a message indicative or confirmative of reservation or releasing of an address of shared memory, and update the probabilistic data structure for the reserved addresses and the released addresses to be considered, as being/not being involved in a current transaction. A method for using the system is provided.

Abstract: An electronic system-level parallel simulation method by means of a multi-core computer system, comprising the parallel evaluation of a plurality of concurrent processes of the simulation on a plurality of cores of the computer system and comprising a sub-method of detection of conflicts of access to a shared memory of a simulated electronic system, the sub-method being implemented by a simulation kernel executed by the computer system and comprises: a step of construction of an oriented graph representative of access to the shared memory by the processes evaluated by the concurrent processes; and a step of detection of loops in the graph; a loop being considered representative of a conflict of access to the shared memory. A computer program product for implementing such a method is provided.

Abstract: A distributed computation system comprising computation units and memory shared between computation units, comprises a hardware module for detecting conflicts of access of computation units to shared memory; each hardware module for detecting conflicts configured to: store a probabilistic data structure, indicative of the addresses of shared memory involved in the current transactions; receive at least one message indicative of request for access, by one computation unit to an address of shared memory; determine, from a probabilistic data structure, whether the address is already involved in a current transaction, and transmit a message indicating presence or absence of access conflicts; receive a message indicative or confirmative of reservation or releasing of an address of shared memory, and update the probabilistic data structure for the reserved addresses and the released addresses to be considered, as being/not being involved in a current transaction. A method for using the system is provided.

Abstract: A method for accelerating the updating of the linking elements in a simulation of a system generated according to a given hardware description language, the method comprising a phase for evaluating the eligible processes of the system, the evaluation phase comprising write or read accesses to linking elements. For each linking element, two write memory locations are provided. The evaluation phase comprises the updating of a linking element for each write or read access of the linking element. The update comprises the following steps: receive a selection word associated with the linking element; select one of the two write locations associated with the linking element depending on the value of the selection word received for the linking element; and update the current value of the linking element based on the write memory location selected.

Abstract: A method for accelerating the updating of the linking elements in a simulation of a system generated according to a given hardware description language, the method comprising a phase for evaluating the eligible processes of the system, the evaluation phase comprising write or read accesses to linking elements. For each linking element, two write memory locations are provided. The evaluation phase comprises the updating of a linking element for each write or read access of the linking element. The update comprises the following steps: receive a selection word associated with the linking element; select one of the two write locations associated with the linking element depending on the value of the selection word received for the linking element; and update the current value of the linking element based on the write memory location selected.