Patents by Inventor Tanio Nagasaki
Tanio Nagasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8624896Abstract: An information processing apparatus including: a plurality of data processing functional blocks each used for carrying out individual data processing; a flow control section configured to execute control of data flows among the data processing functional blocks; and a control section configured to carry out a setting process to set the data processing functional blocks and the flow control section. The control section acquires configuration information in accordance with a task list for data processing to be carried out; carries out the setting process to set the data processing functional blocks and the flow control section on the basis of the acquired configuration information; and constructs a data processing configuration adapted to various kinds of data processing to be carried out.Type: GrantFiled: May 30, 2008Date of Patent: January 7, 2014Assignee: Sony CorporationInventors: Junichi Sakamoto, Masaharu Yoshimori, Tanio Nagasaki, Shinsuke Koyama, Kazumasa Ito, Minoru Takahata, Mikako Hatakenaka, Jin Satoh, Hideshi Yamada, Kenichiro Yokota, Hideki Takeuchi, Hitoshi Ishikawa
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Patent number: 7884825Abstract: An edge function is computed from two vertex coordinates given by a rendering target line. Gradient determination is then performed on the edge function, and the functions representing two shift lines that are formed by translating the rendering target line in the y-axis direction or x-axis direction depending on the angle formed by the rendering target line and the x-axis of the rendering plane coordinate system by 0.5d and ?0.5d will be computed, where d denotes the width of one pixel. Then, the number of subpixels included in a parallelogram, which has four points of the starting points and ending points of the two shift lines as vertices, is acquired so as to determine the pixel value of each pixel based on the number.Type: GrantFiled: October 21, 2005Date of Patent: February 8, 2011Assignee: Sony Computer Entertainment Inc.Inventors: Teruyuki Nakahashi, Tanio Nagasaki, Minoru Takahata
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Patent number: 7697817Abstract: A picture processing apparatus for processing picture signals of different formats. A memory stores input picture signals. A read-out section reads the picture signals stored in the memory in terms of a preset number of the picture signals as a unit. An interpolation section interpolates picture signals for a preset position by executing preset calculations on the plural picture signals read out. For picture signals of an HD format, the picture signals are simultaneously read out in terms of the four pixels as a unit to execute four-point interpolation processing. Whilst for picture signals of an SD format, after a conversion to a 960.times.720 frame picture by applying field/frame conversion and doubling the number of the pixels in the vertical direction, the picture signals are stored in the memory. The operating frequency and the number of times of operations of the read-out section and the interpolation section are changed to values as large as four times those.Type: GrantFiled: September 26, 2001Date of Patent: April 13, 2010Assignee: Sony CorporationInventor: Tanio Nagasaki
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Patent number: 7609263Abstract: A drawing processing apparatus is provided to solve the problems in which pixels of a drawing primitive with sub-pixel information may have an increased amount of data causing a burden on implementation. A setup processing unit sets up various parameters to allow a digital differential analyzer (DDA) to process the stream of a drawing primitive supplied from a primitive input unit. The DDA performs DDA processing on the drawing primitive supplied from the setup processing unit for conversion into pixel data. The DDA performs the DDA processing on a per rectangular pixel set basis along a scan line to output the pixel data of the drawing primitive on a per rectangular pixel set basis. A compression encoding unit encodes the sub-pixel information of each pixel contained in the rectangular pixel set by run length encoding for output to a FIFO buffer.Type: GrantFiled: February 6, 2006Date of Patent: October 27, 2009Assignee: Sony Computer Entertainment Inc.Inventors: Tanio Nagasaki, Teruyuki Nakahashi, Minoru Takahata, Yasuhiro Moriyama
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Publication number: 20080301681Abstract: An information processing apparatus including: a plurality of data processing functional blocks each used for carrying out individual data processing; a flow control section configured to execute control of data flows among the data processing functional blocks; and a control section configured to carry out a setting process to set the data processing functional blocks and the flow control section. The control section acquires configuration information in accordance with a task list for data processing to be carried out; carries out the setting process to set the data processing functional blocks and the flow control section on the basis of the acquired configuration information; and constructs a data processing configuration adapted to various kinds of data processing to be carried out.Type: ApplicationFiled: May 30, 2008Publication date: December 4, 2008Inventors: Junichi Sakamoto, Masaharu Yoshimori, Tanio Nagasaki, Shinsuke Koyama, Kazumasa Ito, Minoru Takahata, Mikako Hatakenaka, Jin Satoh, Hideshi Yamada, Kenichiro Yokota, Hideki Takeuchi, Hitoshi Ishikawa
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Publication number: 20080198163Abstract: An edge function is computed from two vertex coordinates given by a rendering target line 66 as shown in FIG. 8. Gradient determination is then performed on the edge function, and if the acute angle formed by the rendering target line 66 and the x-axis of the rendering plane coordinate system is 45 degrees or less, the functions representing two shift lines 68 that are formed by translating the rendering target line 66 in the y-axis direction by 0.5d and ?0.5d will be computed, where d denotes the width of one pixel. If, on the other hand, the acute angle formed by the rendering target line 66 and the y-axis of the rendering plane coordinate system is more than 45 degrees, the functions representing two shift lines that are formed by translating the rendering target line 66 in the x-axis direction by 0.5d and ?0.5d will be computed.Type: ApplicationFiled: October 21, 2005Publication date: August 21, 2008Applicant: SONY COMPUTER ENTERTAINMENT INC.Inventors: Teruyuki Nakahashi, Tanio Nagasaki, Minoru Takahata
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Patent number: 7280121Abstract: An image processing apparatus capable of realizing accurate anti-aliasing with a small memory, without being affected by the order of drawing, and without inducing a drop in the drawing speed, including an anti-aliasing system obtaining edge information from an image after drawing, determining a processing content necessary for the anti-aliasing, and performing the determined processing. Specifically, either of the information of a z-buffer and the information of the normal vector at each pixel obtained at the time of drawing, or both information, is scanned or by the information of normal vectors restored from the information of the z-buffer is used, a state machine for holding the state and a counter for measuring the continuity of an edge are prescribed, the value of which pixel adjacent in which direction to each pixel on each edge and what kind of ratio to use for blending are determined, and the determined values are used for blending. This is performed successively until the pixel values are updated.Type: GrantFiled: September 23, 2004Date of Patent: October 9, 2007Assignee: Sony CorporationInventors: Teruyuki Nakahashi, Osamu Watanabe, Tanio Nagasaki, Tetsugo Inada, Yasuhiro Moriyama, Hideshi Yamada
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Patent number: 7151862Abstract: Texture data filtered according to each of different reduction ratio are stored in a texture buffer. A texture mapping apparatus (an lod calculating apparatus) calculates an lod (Level Of Detail) which represents a reduction ratio of each pixel of a polygon. The calculation does not include a divisional calculation. In other words, the lod calculating apparatus does not need many multipliers, as compared with a case in which an operation including a divisional calculation, thereby enabling the down-sizing of the lod calculating apparatus.Type: GrantFiled: November 19, 2002Date of Patent: December 19, 2006Assignee: Sony CorporationInventors: Tanio Nagasaki, Hideaki Tomikawa, Seigo Iwasaki, Tetsuo Motomura, Masahiro Igarashi
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Publication number: 20060176316Abstract: A drawing processing apparatus is provided to solve the problems in which pixels of a drawing primitive with sub-pixel information may have an increased amount of data causing a burden on implementation. A setup processing unit sets up various parameters to allow a digital differential analyzer (DDA) to process the stream of a drawing primitive supplied from a primitive input unit. The DDA performs DDA processing on the drawing primitive supplied from the setup processing unit for conversion into pixel data. The DDA performs the DDA processing on a per rectangular pixel set basis along a scan line to output the pixel data of the drawing primitive on a per rectangular pixel set basis. A compression encoding unit encodes the sub-pixel information of each pixel contained in the rectangular pixel set by run length encoding for output to a FIFO buffer.Type: ApplicationFiled: February 6, 2006Publication date: August 10, 2006Inventors: Tanio Nagasaki, Teruyuki Nakahashi, Minoru Takahata, Yasuhiro Moriyama
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Publication number: 20050068326Abstract: An image processing apparatus capable of extracting edge information accurate enough to be able to be utilized for anti-aliasing without rendering of pixels other than the originally necessary drawn pixels and without inducing a drop in the drawing speed, including an anti-aliasing system for restoring edge information for an x-direction and a y-direction in screen coordinates from an image after drawing, determining a processing content necessary for the anti-aliasing from the obtained edge information, and performing the determined processing. Specifically, by scanning either of the information of a z-buffer and the information of the normal vector at each pixel obtained at the time of drawing, or both information, or by using the information of normal vectors restored from the information of the z-buffer, the anti-aliasing is applied to each pixel.Type: ApplicationFiled: September 23, 2004Publication date: March 31, 2005Inventors: Teruyuki Nakahashi, Osamu Watanabe, Tanio Nagasaki, Tetsugo Inada, Yasuhiro Moriyama, Hideshi Yamada
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Publication number: 20050068333Abstract: An image processing apparatus capable of realizing accurate anti-aliasing with a small memory, without being affected by the order of drawing, and without inducing a drop in the drawing speed, including an anti-aliasing system obtaining edge information from an image after drawing, determining a processing content necessary for the anti-aliasing, and performing the determined processing. Specifically, either of the information of a z-buffer and the information of the normal vector at each pixel obtained at the time of drawing, or both information, is scanned or by the information of normal vectors restored from the information of the z-buffer is used, a state machine for holding the state and a counter for measuring the continuity of an edge are prescribed, the value of which pixel adjacent in which direction to each pixel on each edge and what kind of ratio to use for blending are determined, and the determined values are used for blending. This is performed successively until the pixel values are updated.Type: ApplicationFiled: September 23, 2004Publication date: March 31, 2005Inventors: Teruyuki Nakahashi, Osamu Watanabe, Tanio Nagasaki, Tetsugo Inada, Yasuhiro Moriyama, Hideshi Yamada
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Publication number: 20030160894Abstract: A picture processing apparatus for processing picture signals of different formats comprises a memory 20 for storing input picture signals, read-out means 21 for simultaneously reading out the picture signals stored in the memory in terms of a preset number of the picture signals as a unit, and interpolation means 22 for interpolating picture signals for a preset position by executing preset calculations on the plural picture signals read out. For picture signals of an HD format, the picture signals are simultaneously read out in terms of the four pixels as a unit to execute four-point interpolation processing.Type: ApplicationFiled: May 23, 2002Publication date: August 28, 2003Inventor: Tanio Nagasaki
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Patent number: 6603922Abstract: An editing system includes an editing device 1 for editing a plurality of channels of video data, a disk recorder 2 constituted by a disk array having a plurality of disks, and a computer 3. The disk recorder 2 prepares a block map for managing recording areas on the disks so that respective subblock data are recorded at such position that a rotational delay time of a head becomes minimum in accessing the subblock data recorded on the respective disks. The disk recorder 2 then divides pixel data of source video frames into a plurality of subblocks for each frame on the basis of the block map, and records the subblocks so that the subblocks are dispersed on a plurality of different disks.Type: GrantFiled: April 15, 1999Date of Patent: August 5, 2003Assignee: Sony CorporationInventors: Masaaki Shino, Tanio Nagasaki, Yasunobu Kato, Masaki Nishikawa, Noboru Ooya, Masatoshi Imai
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Publication number: 20030117399Abstract: Texture data filtered according to each of different reduction ratio are stored in a texture buffer. A texture mapping apparatus (an lod calculating apparatus) calculates an lod (Level Of Detail) which represents a reduction ratio of each pixel of a polygon. The calculation does not include a divisional calculation. In other words, the lod calculating apparatus does not need many multipliers, as compared with a case in which an operation including a divisional calculation, thereby enabling the down-sizing of the lod calculating apparatus.Type: ApplicationFiled: November 19, 2002Publication date: June 26, 2003Inventors: Tanio Nagasaki, Hideaki Tomikawa, Seigo Iwasaki, Tetsuo Motomura, Masahiro Igarashi