Patents by Inventor Tanvir Ahmed
Tanvir Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240051223Abstract: Various implementations include a fused filament fabrication print head system that includes a nozzle, a heating block, and a cooling element. The nozzle defines a nozzle opening and a filament flow path and is configured to deposit a filament through the nozzle opening. The heating block is coupled to the nozzle such that the filament flow path extends through the heating block. The heating block includes a heating element. The cooling element is spaced apart from the heating block along the filament flow path and is configured to provide localized cooling to a portion of the filament at a location along the filament flow path prior to the heating block. The localized cooling provided by the cooling element preserves the stiffness of the filament and ensures sufficient back pressure to push the filament through the heating block and nozzle opening.Type: ApplicationFiled: July 27, 2023Publication date: February 15, 2024Inventors: Robert Taylor, Rhugdhrivya Rane, Manjarik Mrinal, Parimal Thakorbhai Patel, Tanvir Ahmed Shanto
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Publication number: 20230351030Abstract: Under Backend Application Session Management (“BASM”), a DBMS not only creates an application session but also the respective adjunct security context to which to attach the adjunct security context. The middle tier does not need to create the application session or its adjunct security context. Instead, the middle tier sends an end-user token that the middle tier piggybacks to database requests that are sent through database connections. The end-user token identifies an end user and has been authenticated by the middle tier. The generation of the end-user token is concomitant to the process of the middle tier authenticating the end user. The DBMS invokes a user-defined function to generate an adjunct security context. The user-defined function generates the adjunct security context based on the end-user token. Application developers can customize the user-defined function to customize backend security for their needs.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Inventors: MINCAI ANDREW WANG, CHAO LIANG, TANVIR AHMED
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Publication number: 20230252275Abstract: Neural network hardware acceleration data parallelism is performed by an integrated circuit including a plurality of memory banks, each memory bank among the plurality of memory banks configured to store values and to transmit stored values, a plurality of computation units, each computation unit among the plurality of computation units including one of a channel pipeline and a multiply-and-accumulate (MAC) element configured to perform a mathematical operation on an input data value and a weight value to produce a resultant data value, and a computation controller configured to cause a value transmission to be received by more than one computation unit or memory bank.Type: ApplicationFiled: April 13, 2023Publication date: August 10, 2023Inventors: Nikolay NEZ, Oleg KHAVIN, Tanvir AHMED, Jens HUTHMANN, Sakyasingha DASGUPTA
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Patent number: 11657260Abstract: Neural network hardware acceleration data parallelism is performed by an integrated circuit including a plurality of memory banks, each memory bank among the plurality of memory banks configured to store values and to transmit stored values, a plurality of computation units, each computation unit among the plurality of computation units including a processor including circuitry configured to perform a mathematical operation on an input data value and a weight value to produce a resultant data value, and a computation controller configured to cause a value transmission to be received by more than one computation unit or memory bank.Type: GrantFiled: October 26, 2021Date of Patent: May 23, 2023Assignee: EDGECORTIX PTE. LTD.Inventors: Nikolay Nez, Oleg Khavin, Tanvir Ahmed, Jens Huthmann, Sakyasingha Dasgupta
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Publication number: 20230128600Abstract: Neural network hardware acceleration data parallelism is performed by an integrated circuit including a plurality of memory banks, each memory bank among the plurality of memory banks configured to store values and to transmit stored values, a plurality of computation units, each computation unit among the plurality of computation units including a processor including circuitry configured to perform a mathematical operation on an input data value and a weight value to produce a resultant data value, and a computation controller configured to cause a value transmission to be received by more than one computation unit or memory bank.Type: ApplicationFiled: October 26, 2021Publication date: April 27, 2023Inventors: Nikolay NEZ, Oleg KHAVIN, Tanvir AHMED, Jens HUTHMANN, Sakyasingha DASGUPTA
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Publication number: 20230079703Abstract: The present disclosure provides compositions and methods useful for inducing a The cell response in a subject suffering from Hepatitis B. As described herein, the compositions of the disclosure comprise HBsAg having S, Pre-S1 and Pre-S2 proteins and an aluminum phosphate adjuvant. In a preferred embodiment, the immunogenic composition comprises at least 20 ?g/ml of HBsAg antigen and the amount of non-adsorbed antigen is at least 30%.Type: ApplicationFiled: November 13, 2019Publication date: March 16, 2023Inventors: David Evander ANDERSON, Tanvir AHMED
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Patent number: 11481618Abstract: Arithmetic processing units individually compute values of a predetermined number of neurons amongst a plurality of neurons in a neural network, where the predetermined number of neurons belong to each arithmetic processing unit, and each of the predetermined number of neurons belonging to an arithmetic processing unit is connected to every other neuron belonging thereto. A control unit causes each arithmetic processing unit to perform the computation by providing dense-connection weight coefficients, which correspond to a dense-connection part of the evaluation function, associated with every connection of two neurons belonging thereto. The control unit calculates changes in energy using sparse-connection weight coefficients, which correspond to a sparse-connection part of the evaluation function, individually associated with a connection of two neurons belonging to different arithmetic processing units.Type: GrantFiled: February 25, 2019Date of Patent: October 25, 2022Assignee: FUJITSU LIMITEDInventor: Tanvir Ahmed
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Publication number: 20220302926Abstract: A data processing method includes: acquiring, by one or more processors, compressed data generated from data, wherein values of the compressed data are stored at first storage locations, values of the data are stored at second storage locations; acquiring, by the one or more processors, index data includes indices indicative of the first storage locations; acquiring, by the one or more processors, at least two packed indices from the index data, the at least two packed indices being generated from the index data; and inputting, by the one or more processors, the at least two packed indices into at least two selectors.Type: ApplicationFiled: June 8, 2022Publication date: September 22, 2022Inventor: Tanvir AHMED
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Patent number: 11387844Abstract: One aspect of the present disclosure relates to a data compression method. The method includes generating, by one or more processors, compressed data from data, wherein the compressed data includes one or more unduplicated values of the data and generating, by the one or more processors, index data from the data, wherein the index data includes indices indicative of storage locations for the unduplicated values.Type: GrantFiled: April 2, 2020Date of Patent: July 12, 2022Assignee: Preferred Networks, Inc.Inventor: Tanvir Ahmed
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Patent number: 11386221Abstract: Embodiments allow, within database security policies, the grant of data change operation-specific privileges to particular users to be applied within particular data realms in a given table. Furthermore, according to one or more embodiments, User Privilege column-level privileges are explicitly associated with one or more data access operations such that the grant of such a column-level privilege allows the user to perform only those data access operations that are explicitly associated with the column-level privilege. Enforcement of the data security policies includes prevention of data leakage via WHERE and RETURNING INTO clauses. According to one or more embodiments, a two-phase rewrite is used to optimize enforcement of column-level privileges. During the two-phase rewrite of a given query, the privileges checked during enforcement of the User Privilege data security policies are pruned to avoid unnecessary privilege checks given the columns that are accessed in the query.Type: GrantFiled: April 15, 2019Date of Patent: July 12, 2022Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Tanvir Ahmed, Yi Ru, Chao Liang, Vikram Reddy Pesati
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Patent number: 11360788Abstract: A configuration control transfer (“CCT”) system controls the transferring of control of configuration information of a device from a current configuration source to a target configuration source. A CCT server of the CCT system may send a request for the configuration information of the device where the configuration information of the device currently under control of the at least one first configuration source. The CCT server may also receive the requested configuration information, determine whether the second configuration source is able to support the configuration information of the first configuration source, and based at least on a determination that the second configuration source is able to support the configuration information, request that the device transfer control of the configuration information from the first configuration source to the second configuration source to unenroll the device with the first configuration source and enroll the device with the second configuration source.Type: GrantFiled: March 31, 2020Date of Patent: June 14, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Tanvir Ahmed, Peter J. Kaufman, Shayak Lahiri, John Chadwell Spaith, Janani Vasudevan, Dennis Edward Flanagan
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Publication number: 20210406010Abstract: A processor having a systolic array that can perform operations efficiently is provided. The processor includes multiple processing cores aligned in a matrix, and each of the processing cores includes an arithmetic unit array including multiple arithmetic units that can form a systolic array. Each of the processing cores includes a first memory that stores first data, a second memory that stores second data, a first multiplexer that connects a first input for receiving the first data at the arithmetic unit array to an output of the first memory in the processing core or an output of the arithmetic unit array in an adjacent processing core, and a second multiplexer that connects a second input for receiving the second data at the arithmetic unit array to an output of the second memory in the processing core or an output of the arithmetic unit array in an adjacent processing core.Type: ApplicationFiled: September 10, 2021Publication date: December 30, 2021Inventor: Tanvir AHMED
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Publication number: 20210288650Abstract: A semiconductor device includes multiple reconfiguration blocks arranged in a first direction, logic of the multiple reconfiguration blocks being reconfigurable, multiple non-reconfiguration blocks disposed between the multiple reconfiguration blocks, each of the multiple non-reconfiguration blocks including multiple first arithmetic units, and logic of the multiple first arithmetic units being not reconfigurable, and multiple processing units implemented in the multiple reconfiguration blocks and the multiple non-reconfiguration blocks in a matrix form, the multiple processing units including second arithmetic units.Type: ApplicationFiled: March 12, 2021Publication date: September 16, 2021Inventors: Tanvir AHMED, Ken NAMURA
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Patent number: 11119765Abstract: A processor having a systolic array that can perform operations efficiently is provided. The processor includes multiple processing cores aligned in a matrix, and each of the processing cores includes an arithmetic unit array including multiple arithmetic units that can form a systolic array. Each of the processing cores includes a first memory that stores first data, a second memory that stores second data, a first multiplexer that connects a first input for receiving the first data at the arithmetic unit array to an output of the first memory in the processing core or an output of the arithmetic unit array in an adjacent processing core, and a second multiplexer that connects a second input for receiving the second data at the arithmetic unit array to an output of the second memory in the processing core or an output of the arithmetic unit array in an adjacent processing core.Type: GrantFiled: November 1, 2019Date of Patent: September 14, 2021Assignee: Preferred Networks, Inc.Inventor: Tanvir Ahmed
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Publication number: 20210125064Abstract: Techniques for training neural networks in accordance with an adaptive loss scaling scheme are disclosed. One aspect of the present disclosure relates to a method of training a neural network including a plurality of layers, including determining, by one or more processors, layer-wise loss scale factors for the respective layers and updating, by the one or more processors, parameters for the layers in accordance with error gradients for the layers, wherein the error gradients are scaled with the corresponding layer-wise loss scale factors.Type: ApplicationFiled: October 19, 2020Publication date: April 29, 2021Inventors: Ruizhe ZHAO, Brian VOGEL, Tanvir AHMED
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Publication number: 20200336152Abstract: One aspect of the present disclosure relates to a data compression method. The method includes generating, by one or more processors, compressed data from data, wherein the compressed data includes one or more unduplicated values of the data and generating, by the one or more processors, index data from the data, wherein the index data includes indices indicative of storage locations for the unduplicated values.Type: ApplicationFiled: April 2, 2020Publication date: October 22, 2020Inventor: Tanvir AHMED
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Publication number: 20200257542Abstract: A configuration control transfer (“CCT”) system controls the transferring of control of configuration information of a device from a current configuration source to a target configuration source. A CCT server of the CCT system may send a request for the configuration information of the device where the configuration information of the device currently under control of the at least one first configuration source. The CCT server may also receive the requested configuration information, determine whether the second configuration source is able to support the configuration information of the first configuration source, and based at least on a determination that the second configuration source is able to support the configuration information, request that the device transfer control of the configuration information from the first configuration source to the second configuration source to unenroll the device with the first configuration source and enroll the device with the second configuration source.Type: ApplicationFiled: March 31, 2020Publication date: August 13, 2020Applicant: Microsoft Technology Licensing, LLCInventors: Tanvir Ahmed, Peter J. Kaufman, Shayak Lahiri, John Chadwell Spaith, Janani Vasudevan, Dennis Edward Flanagan
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Patent number: 10736844Abstract: The present disclosure provides compositions and methods useful for treating viral infections. As described herein, the compositions and methods are based on the development of immunogenic compositions that include an attenuated or inactivated virus in combination with a non-ionic surfactant vesicle (NISV).Type: GrantFiled: January 13, 2012Date of Patent: August 11, 2020Assignee: VARIATION BIOTECHNOLOGIES INC.Inventors: David E. Anderson, Tanvir Ahmed, Jasminka Bozic, Marc Kirchmeier
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Publication number: 20200150958Abstract: A processor having a systolic array that can perform operations efficiently is provided. The processor includes multiple processing cores aligned in a matrix, and each of the processing cores includes an arithmetic unit array including multiple arithmetic units that can form a systolic array. Each of the processing cores includes a first memory that stores first data, a second memory that stores second data, a first multiplexer that connects a first input for receiving the first data at the arithmetic unit array to an output of the first memory in the processing core or an output of the arithmetic unit array in an adjacent processing core, and a second multiplexer that connects a second input for receiving the second data at the arithmetic unit array to an output of the second memory in the processing core or an output of the arithmetic unit array in an adjacent processing core.Type: ApplicationFiled: November 1, 2019Publication date: May 14, 2020Inventor: Tanvir AHMED
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Patent number: 10628174Abstract: A configuration control transfer (“CCT”) system controls the transferring of control of configuration information of a device from a current configuration source to a target configuration source. A CCT server of the CCT system may send to the device a message requesting the configuration information of the device. In response, a CCT client of the CCT system collects the configuration information of the device and sends the collected configuration information to the CCT server. If the second configuration source can support the configuration information of the current configuration source, the CCT server requests that the device transfer control of the configuration information from the current configuration source to the target configuration source. The CCT client then transfers control of the configuration information to the target configuration source as the new current configuration source and un-enrolls the device from the former current configuration source.Type: GrantFiled: February 17, 2016Date of Patent: April 21, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Tanvir Ahmed, Peter J. Kaufman, Shayak Lahiri, John Chadwell Spaith, Janani Vasudevan, Dennis Edward Flanagan