Patents by Inventor Tao-Cheng Lu
Tao-Cheng Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8937347Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.Type: GrantFiled: April 30, 2014Date of Patent: January 20, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
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Patent number: 8929134Abstract: A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line to a first voltage, biasing a string select transistor to a second voltage; and ramping down the string select transistor to the first voltage. In particular, the second voltage is higher than the first voltage.Type: GrantFiled: February 8, 2013Date of Patent: January 6, 2015Assignee: Macronix International Co., Ltd.Inventors: Chu Yung Liu, Hsing Wen Chang, Yao Wen Chang, Tao Cheng Lu
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Publication number: 20140269054Abstract: A method of altering threshold voltage distribution of a non-volatile MLC memory before the memory is programmed according to a pre-designated coding table. The method includes grouping a plurality of cells which are pre-designated to have the same first bit voltage in a same main state and then grouping the cells in a selected main state into a same sub state if they have the same pre-designated second bit voltage. The method further has a step by elevating the first bit voltage of the cells with highest pre-designated second bit voltage to a voltage which is greater than the voltage of the pre-designated highest main state.Type: ApplicationFiled: April 3, 2013Publication date: September 18, 2014Applicant: Macronix International Co., Ltd.Inventors: GUAN WEI WU, YAO WEN CHANG, I CHEN YANG, TAO CHENG LU
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Publication number: 20140264528Abstract: A non-volatile memory structure includes a source and a drain. The memory structure includes a substrate and a dielectric layer on the substrate. The memory structure further has a gate, which can be a floating gate, on the dielectric layer. A recess is on the drain side and nearest to the bottom corner of the dielectric layer. The recess is configured to reduce the electric field density around the bottom corner nearest to the drain in order to reduce the damage on the dielectric layer when the memory is under a bias.Type: ApplicationFiled: May 2, 2013Publication date: September 18, 2014Applicant: MACRONIX International Co., Ltd.Inventors: TAO YUAN LIN, CHEN HAN CHOU, I CHEN YANG, YAO WEN CHANG, TAO CHENG LU
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Publication number: 20140264378Abstract: A semiconductor structure has a MOSFET and a substrate to accommodate the MOSFET. The MOSFET has a gate, a source, and a drain in the substrate. A first substrate region surrounding the MOSFET is doped with a stress enhancer, wherein the stress enhancer is configured to generate a tensile stress in the MOSFET's channel and the tensile stress is along the channel's widthwise direction.Type: ApplicationFiled: April 2, 2013Publication date: September 18, 2014Applicant: MACRONIX International Co., Ltd.Inventors: GUAN WEI WU, YAO WEN CHANG, I CHEN YANG, TAO CHENG LU
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Patent number: 8836005Abstract: A memory array includes a charge storage structure and a plurality of conductive materials over the charge storage structure is provided. Each conductive material, serving as a word line, has a substantially arc-sidewall and a substantially straight sidewall.Type: GrantFiled: August 24, 2010Date of Patent: September 16, 2014Assignee: MACRONIX International Co., Ltd.Inventors: I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
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Publication number: 20140231900Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.Type: ApplicationFiled: April 30, 2014Publication date: August 21, 2014Applicant: MACRONIX International Co., Ltd.Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
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Publication number: 20140226411Abstract: A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line to a first voltage, biasing a string select transistor to a second voltage; and ramping down the string select transistor to the first voltage. In particular, the second voltage is higher than the first voltage.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: CHU YUNG LIU, HSING WEN CHANG, YAO WEN CHANG, TAO CHENG LU
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Publication number: 20140159134Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.Type: ApplicationFiled: December 6, 2012Publication date: June 12, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
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Patent number: 8748963Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory including a gate structure disposed on a substrate, doped regions, charge storage layers, and a first dielectric layer. There are recesses in the substrate at two sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate and a gate disposed on the gate dielectric layer. There is an interface between the gate dielectric layer and the substrate. The doped regions are disposed in the substrate around the recesses. The charge storage layers are disposed in the recesses, and a top surface of each of the charge storage layers is higher than the interface. The first dielectric layer is disposed between the charge storage layers and the substrate, and between the charge storage layers and the gate structure.Type: GrantFiled: December 6, 2012Date of Patent: June 10, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
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Patent number: 8748936Abstract: A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region.Type: GrantFiled: July 20, 2012Date of Patent: June 10, 2014Assignee: Macronix International Co., Ltd.Inventors: Shih-Yu Wang, Chia-Ling Lu, Yan-Yu Chen, Yu-Lien Liu, Tao-Cheng Lu
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Publication number: 20140092504Abstract: An electrostatic discharge protection device including a silicon-controlled rectifier and a path switching circuit is provided. The silicon-controlled rectifier includes a first connection terminal, a second connection terminal, a first control terminal and a second control terminal, wherein the first connection terminal and the second connection terminal are respectively connected to a first line and a second line. The path switching circuit is electrically connected to the first line, the first control terminal and the second control terminal. When an input signal is supplied to the first line, the path switching circuit provides a first current path from the first line to the first control terminal in response to the input signal. When an electrostatic pulse is appeared on the first line, the path switching circuit provides a second current path from the first control terminal to the second control terminal in response to the electrostatic pulse.Type: ApplicationFiled: October 3, 2012Publication date: April 3, 2014Applicant: MACRONIX International Co., Ltd.Inventors: Shih-Yu Wang, Yao-Wen Chang, Tao-Cheng Lu
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Patent number: 8675322Abstract: An electrostatic discharge (ESD) protection device electronically connected to a pad is provided. The ESD protection device includes K PNP transistors and a protection circuit, wherein K is a positive integer. An emitter of the 1st PNP transistor is electronically connected to the pad, a base of the ith PNP transistor is electronically connected to an emitter of the (i+1)th PNP transistor, and collectors of the K PNP transistors are electronically connected to a ground, wherein i is an integer and 1?i?(K?1). The protection circuit is electronically connected between a base of the Kth PNP transistor and the ground and provides a discharge path. An electrostatic signal from the pad is conducted to the ground through the discharge path and the K PNP transistors.Type: GrantFiled: May 11, 2011Date of Patent: March 18, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Shih-Yu Wang, Yao-Wen Chang, Tao-Cheng Lu
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Patent number: 8605507Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a program bias pulse by biasing the bit lines and string select lines in a first condition; setting a word line coupled to a target cell to a first voltage level while the bit lines and string select lines are in the first condition; thereafter, biasing the bit lines and string select lines in a second condition; and setting the word line coupled to the target cell to a second voltage level higher than the first voltage level while the bit lines and string select lines are in the second condition. Program bias pulses produced in this manner can be used in a modulated incremental stepped pulse programming sequence.Type: GrantFiled: January 12, 2012Date of Patent: December 10, 2013Assignee: Macronix International Co., Ltd.Inventors: Chuyung Liu, Hsing-Wen Chang, Yaowen Chang, Tao-Cheng Lu
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Patent number: 8501591Abstract: A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.Type: GrantFiled: November 21, 2005Date of Patent: August 6, 2013Assignee: Macronix International Co., Ltd.Inventors: Chih Chieh Yeh, Han Chao Lai, Wen Jer Tsai, Tao Cheng Lu, Chih Yuan Lu
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Publication number: 20130182505Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a program bias pulse by biasing the bit lines and string select lines in a first condition; setting a word line coupled to a target cell to a first voltage level while the bit lines and string select lines are in the first condition; thereafter, biasing the bit lines and string select lines in a second condition; and setting the word line coupled to the target cell to a second voltage level higher than the first voltage level while the bit lines and string select lines are in the second condition. Program bias pulses produced in this manner can be used in a modulated incremental stepped pulse programming sequence.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Applicant: Macronix International Co., Ltd.Inventors: Chuyung Liu, Hsing-Wen Chang, Yaowen Chang, Tao-Cheng Lu
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Patent number: 8411506Abstract: A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell.Type: GrantFiled: November 18, 2010Date of Patent: April 2, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
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Patent number: 8345396Abstract: An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.Type: GrantFiled: March 8, 2010Date of Patent: January 1, 2013Assignee: Macronix International Co., Ltd.Inventors: Shih-Yu Wang, Chia-Ling Lu, Yu-Lien Liu, Yan-Yu Chen, Che-Shih Lin, Tao-Cheng Lu
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Patent number: 8338880Abstract: A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion.Type: GrantFiled: July 12, 2010Date of Patent: December 25, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
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Publication number: 20120287539Abstract: An electrostatic discharge (ESD) protection device electronically connected to a pad is provided. The ESD protection device includes K PNP transistors and a protection circuit, wherein K is a positive integer. An emitter of the 1st PNP transistor is electronically connected to the pad, a base of the ith PNP transistor is electronically connected to an emitter of the (i+1)th PNP transistor, and collectors of the K PNP transistors are electronically connected to a ground, wherein i is an integer and 1?i?(K?1). The protection circuit is electronically connected between a base of the Kth PNP transistor and the ground and provides a discharge path. An electrostatic signal from the pad is conducted to the ground through the discharge path and the K PNP transistors.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shih-Yu Wang, Yao-Wen Chang, Tao-Cheng Lu