Patents by Inventor Tao Shinn Chen

Tao Shinn Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6003038
    Abstract: A class structure of an object-oriented program system is optimized for hardware and implemented as a hardware system in an object-oriented processor. For example, a class structure derived from a Java Virtual Machine software system is optimized for hardware and implemented as a hardware Java object-oriented processor. A processor is implemented by defining a data structure and an object-oriented instruction set for executing in the object-oriented operating environment, and generating a hardware implementation of the processor enforcing the logical relationships of the instruction set as defined by the data structure. The data structure includes a class structure. The class structure and the instruction set describe the processor operations. A processor includes an execution engine based on a class structure to execute instructions of an object-oriented instruction set. The instruction set uses pointers for indexing through data structures to define an object method for execution.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: December 14, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Tao Shinn Chen
  • Patent number: 5970240
    Abstract: A configurable method and apparatus for implementing the various large memory instances commonly found in a user's design in a hardware logic emulation system is disclosed. No external boards or systems are required to implement typical memory instances. The method and apparatus sorts the memory instances in the user's input design, packing as many memory instances as possible into a physical RAM on the emulation boards. The method also counts the number of physical RAMs necessary to implement the plurality of memory instances. The method maps the memory instances into physical RAMs, and routes the address, data and control signals and controller circuit into a programmable logic chip.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: October 19, 1999
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Tao Shinn Chen, Dam Van Bui