Patents by Inventor Tao-Wen Chung
Tao-Wen Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10546528Abstract: A current value of a first pixel and/or a current value of a second pixel of a display are adjusted until a value of a current difference is within a predetermined range. The current value of the first pixel corresponds to a brightness level of the first pixel. The current value of the second pixel corresponds to a brightness level of the second pixel. Adjusting the current value of the first pixel involves adjusting a threshold voltage value of a transistor of the first pixel. Adjusting the current value of the second pixel involves adjusting a threshold voltage value of a transistor of the second pixel.Type: GrantFiled: August 14, 2015Date of Patent: January 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching Huang, Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin
-
Patent number: 9755429Abstract: A method of increasing a current flowing through an inductor includes receiving an input signal with a driver stage, the driver stage including the inductor coupled in series with a loading between an output node of the driver stage and a power line. In response to a transition in the input signal from a first voltage state to a second voltage state, a first current flowing through the loading and the inductor is increased. During the transition in the input signal, the current flowing through the inductor is increased by increasing a second current in a circuitry though a node between the inductor and the loading.Type: GrantFiled: November 17, 2015Date of Patent: September 5, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
-
Patent number: 9722818Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.Type: GrantFiled: September 22, 2014Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen Chung, Yuwen Swei, Chih-Chang Lin, Tsung-Ching Huang
-
Patent number: 9509260Abstract: A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to receive an input signal. A second inverter has a second input node and a second output node. The second input node connects to a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node. A first amplifier is configured to provide feedback to the first input node and a second amplifier is configured to provide feedback to the second input node.Type: GrantFiled: October 1, 2014Date of Patent: November 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Ching Huang, Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin
-
Patent number: 9461539Abstract: A voltage regulator includes a driving circuit, a feedback circuit, first and second control circuits and a resistor. The driving circuit is coupled to an input node and an output node and generates an output voltage at the output node from an input voltage at the input node. The feedback circuit is coupled to the output node and generates a feedback voltage based on the output voltage. The first control circuit is coupled to the feedback circuit and the driving circuit to control the output voltage based on the feedback voltage. The resistor has opposite first and second terminals. The first terminal of the resistor is coupled to the output node. The second control circuit is coupled to the second terminal of the output stage resistor and the feedback circuit to control the feedback voltage based on a regulated voltage at the second terminal of the resistor.Type: GrantFiled: March 15, 2013Date of Patent: October 4, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching (Jim) Huang
-
Patent number: 9450789Abstract: An apparatus includes a plurality of delay elements configured to delay a respective input signal and to output a respective delayed signal. The apparatus also includes a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further includes a tap controller configured to generate tap weight enabling signals corresponding to one or more of the tap weights if the corresponding tap weights are greater than a predetermined threshold value. The tap controller is also configured to generate a set of bias factors based on corresponding tap weights of the plurality of tap weights.Type: GrantFiled: July 9, 2015Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh Huang, Jing Jing Chen, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Yuwen Swei
-
Patent number: 9437257Abstract: A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.Type: GrantFiled: February 12, 2013Date of Patent: September 6, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tien-Chun Yang, Yue-Der Chih, Chan-Hong Chern, Tao Wen Chung
-
Patent number: 9391626Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.Type: GrantFiled: August 11, 2014Date of Patent: July 12, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching Huang, Fu-Lung Hsueh
-
Patent number: 9348965Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.Type: GrantFiled: November 17, 2014Date of Patent: May 24, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Sheng Chen, Tsun-Yu Yang, Wei-Yi Hu, Tao Wen Chung, Jui-Feng Kuan, Yi-Kan Cheng
-
Publication number: 20160087817Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.Type: ApplicationFiled: September 22, 2014Publication date: March 24, 2016Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Yuwen SWEI, Chih-Chang LIN, Tsung-Ching HUANG
-
Publication number: 20160072279Abstract: A method of increasing a current flowing through an inductor includes receiving an input signal with a driver stage, the driver stage including the inductor coupled in series with a loading between an output node of the driver stage and a power line. In response to a transition in the input signal from a first voltage state to a second voltage state, a first current flowing through the loading and the inductor is increased. During the transition in the input signal, the current flowing through the inductor is increased by increasing a second current in a circuitry though a node between the inductor and the loading.Type: ApplicationFiled: November 17, 2015Publication date: March 10, 2016Inventors: Tao Wen CHUNG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Yuwen SWEI
-
Patent number: 9276537Abstract: A method of sharing inductors for inductive peaking of an amplifier includes calculating a single stage inductance of a single stage for inductive peaking in order to have a stable impulse response. The method further includes determining a number of stages for shared inductance for inductive peaking. The method further includes sharing at least two inductors having the shared inductance among the determined number of stages for inductive peaking.Type: GrantFiled: November 25, 2013Date of Patent: March 1, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
-
Patent number: 9214805Abstract: An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. The circuitry comprises at least one pre-driver stage having at least one output node, and the at least one output node of the at least one pre-driver stage is electrically coupled with at least one input node of a driver stage.Type: GrantFiled: December 9, 2013Date of Patent: December 15, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
-
Publication number: 20150356917Abstract: A current value of a first pixel and/or a current value of a second pixel of a display are adjusted until a value of a current difference is within a predetermined range. The current value of the first pixel corresponds to a brightness level of the first pixel. The current value of the second pixel corresponds to a brightness level of the second pixel. Adjusting the current value of the first pixel involves adjusting a threshold voltage value of a transistor of the first pixel. Adjusting the current value of the second pixel involves adjusting a threshold voltage value of a transistor of the second pixel.Type: ApplicationFiled: August 14, 2015Publication date: December 10, 2015Inventors: Tsung-Ching HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Ming-Chieh HUANG, Chih-Chang LIN
-
Patent number: 9197195Abstract: A driver includes a first driver stage having a first T-coil structure. The first T-coil structure includes a first set of inductors each being operable to provide a first inductance. The first T-coil structure further includes a second set of inductors electrically coupled with the first set of inductors, wherein the second set of inductors each are operable to provide a second inductance.Type: GrantFiled: October 22, 2014Date of Patent: November 24, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh Huang, Tao Wen Chung, Chan-Hong Chern, Chih-Chang Lin, Yuwen Swei, Chiang Pu
-
Publication number: 20150319017Abstract: An apparatus includes a plurality of delay elements configured to delay a respective input signal and to output a respective delayed signal. The apparatus also includes a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further includes a tap controller configured to generate tap weight enabling signals corresponding to one or more of the tap weights if the corresponding tap weights are greater than a predetermined threshold value. The tap controller is also configured to generate a set of bias factors based on corresponding tap weights of the plurality of tap weights.Type: ApplicationFiled: July 9, 2015Publication date: November 5, 2015Inventors: Ming-Chieh HUANG, Jing Jing CHEN, Chan-Hong CHERN, Tao Wen CHUNG, Chih-Chang LIN, Yuwen SWEI
-
Patent number: 9134360Abstract: A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.Type: GrantFiled: July 12, 2012Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
-
Patent number: 9094249Abstract: An apparatus comprises a plurality of delay elements connected in series. Each delay element is configured to delay a respective input signal and to output a respective delayed signal. The apparatus also comprises a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further comprises a tap controller configured to (1) generate tap weight enabling signals corresponding to one or more of the tap weights based on a determination that the corresponding tap weights are greater than a predetermined threshold value, and (2) generate a set of bias factors. The apparatus additionally comprises a summer configured to output a weighted signal based on the delayed signals, the tap weight enabling signals, the tap weights, and the bias factors.Type: GrantFiled: January 22, 2015Date of Patent: July 28, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh Huang, Jing Jing Chen, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Yuwen Swei
-
Publication number: 20150131711Abstract: An apparatus comprises a plurality of delay elements connected in series. Each delay element is configured to delay a respective input signal and to output a respective delayed signal. The apparatus also comprises a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further comprises a tap controller configured to (1) generate tap weight enabling signals corresponding to one or more of the tap weights based on a determination that the corresponding tap weights are greater than a predetermined threshold value, and (2) generate a set of bias factors. The apparatus additionally comprises a summer configured to output a weighted signal based on the delayed signals, the tap weight enabling signals, the tap weights, and the bias factors.Type: ApplicationFiled: January 22, 2015Publication date: May 14, 2015Inventors: Ming-Chieh HUANG, Jing Jing CHEN, Chan-Hong CHERN, Tao Wen CHUNG, Chih-Chang LIN, Yuwen SWEI
-
Publication number: 20150074629Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.Type: ApplicationFiled: November 17, 2014Publication date: March 12, 2015Inventors: Chin-Sheng CHEN, Tsun-Yu YANG, Wei -Yi HU, Tao Wen CHUNG, Jui-Feng KUAN, Yi-Kan CHENG