Patents by Inventor Tapas Nandy
Tapas Nandy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10033518Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.Type: GrantFiled: September 13, 2017Date of Patent: July 24, 2018Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Tapas Nandy, Nitin Gupta
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Patent number: 10024888Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.Type: GrantFiled: June 9, 2017Date of Patent: July 17, 2018Assignee: STMicroelectronics International N.V.Inventors: Daljeet Kumar, Tapas Nandy, Surendra Kumar
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Patent number: 9890063Abstract: The present invention relates to provide a carbon bed electrolyzer (CBE) unit for electrochemical treatment. More particularly the present invention relates to the treatment of recalcitrant wastewater, e.g. from chemical industry. Further the said CBE unit is useful for electrolytic treatment of liquid effluent having very high concentrations of Chemical oxygen Demand (COD), Total Kjeldahl Nitrogen (TKN) and Biochemical Oxygen Demand (BOD), and Total Dissolved Solids (TDS), and for improving biodegradability of the effluent. More particularly, the present invention relates to an electro oxidation process wherein the carbon bed gets regenerated in-situ continuously.Type: GrantFiled: March 21, 2011Date of Patent: February 13, 2018Assignee: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCHInventors: Nageswara Rao Neti, Tapas Nandy
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Publication number: 20180006797Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.Type: ApplicationFiled: September 13, 2017Publication date: January 4, 2018Inventors: Tapas NANDY, Nitin GUPTA
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Patent number: 9832008Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.Type: GrantFiled: December 31, 2015Date of Patent: November 28, 2017Assignee: STMicroelectronics International N.V.Inventors: Abhishek Chowdhary, Vivek Uppal, Alok Kaushik, Sajal Kumar Mandal, Tapas Nandy, Sanjeev Chopra
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Patent number: 9794054Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.Type: GrantFiled: June 30, 2015Date of Patent: October 17, 2017Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Tapas Nandy, Nitin Gupta
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Publication number: 20170276710Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.Type: ApplicationFiled: June 9, 2017Publication date: September 28, 2017Inventors: Daljeet Kumar, Tapas Nandy, Surendra Kumar
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Patent number: 9705665Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.Type: GrantFiled: January 28, 2016Date of Patent: July 11, 2017Assignee: STMicroelectronics International N.V.Inventors: Abhishek Chowdhary, Vivek Uppal, Alok Kaushik, Sajal Kumar Mandal, Tapas Nandy, Sanjeev Chopra
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Patent number: 9696351Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.Type: GrantFiled: December 30, 2014Date of Patent: July 4, 2017Assignee: STMicroelectronics International N.V.Inventors: Daljeet Kumar, Tapas Nandy, Surendra Kumar
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Patent number: 9647699Abstract: A power harvesting circuit for use in an open drain transmitter circuit is configured to generate two distinct harvested supply voltages at different voltage levels along with two distinct cascode voltages at different voltage levels. The harvested supply voltages are used to power circuitry in the transmitter circuit. The cascode voltages are used to bias cascode transistors in the open drain circuitry for different channels.Type: GrantFiled: December 30, 2015Date of Patent: May 9, 2017Assignee: STMicroelectronics International N.V.Inventors: Nitin Gupta, Tapas Nandy
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Publication number: 20170005780Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: Tapas Nandy, Nitin Gupta
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Patent number: 9425781Abstract: A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal.Type: GrantFiled: March 31, 2014Date of Patent: August 23, 2016Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Tapas Nandy, Anchal Jain
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Publication number: 20160187392Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.Type: ApplicationFiled: December 30, 2014Publication date: June 30, 2016Inventors: Daljeet KUMAR, Tapas NANDY, Surendra KUMAR
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Patent number: 9356770Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.Type: GrantFiled: March 31, 2014Date of Patent: May 31, 2016Assignee: STMicroelectronics International N.V.Inventors: Abhishek Chowdhary, Vivek Uppal, Alok Kaushik, Sajal Kumar Mandal, Tapas Nandy, Sanjeev Chopra
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Publication number: 20160149695Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.Type: ApplicationFiled: January 28, 2016Publication date: May 26, 2016Inventors: Abhishek CHOWDHARY, Vivek UPPAL, Alok KAUSHIK, Sajal Kumar MANDAL, Tapas NANDY, Sanjeev CHOPRA
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Patent number: 9331671Abstract: A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.Type: GrantFiled: May 20, 2014Date of Patent: May 3, 2016Assignee: STMicroelectronics International N.V.Inventors: Nitin Gupta, Paramjeet Singh Sahni, Tapas Nandy, Manish Garg
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Publication number: 20160119117Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.Type: ApplicationFiled: December 31, 2015Publication date: April 28, 2016Inventors: Abhishek CHOWDHARY, Vivek UPPAL, Alok KAUSHIK, Sajal Kumar MANDAL, Tapas NANDY, Sanjeev CHOPRA
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Publication number: 20150341017Abstract: A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.Type: ApplicationFiled: May 20, 2014Publication date: November 26, 2015Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nitin GUPTA, Paramjeet Singh SAHNI, Tapas NANDY, Manish GARG
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Publication number: 20150280898Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Applicant: STMicroelectronics International N.V.Inventors: Abhishek Chowdhary, Vivek Uppal, Alok Kaushik, Sajal Kumar Mandal, Tapas Nandy, Sanjeev Chopra
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Patent number: 9148099Abstract: An embodiment of a transmitter includes an amplifier having first and second differential output nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential output node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential output node and having a second node coupled to the supply node. An embodiment of a receiver includes an amplifier having first and second differential input nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential input node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential input node and having a second node coupled to the supply node. In an embodiment, the transmitter and receiver are capacitively coupled to one another.Type: GrantFiled: December 29, 2010Date of Patent: September 29, 2015Assignee: STMicroelectronics International N.V.Inventors: Tapas Nandy, Nitin Gupta