Abstract: An image processor that can reduce in capacity of a B-picture memory is disclosed. The B-picture memory stores luminance data and color-difference data of decoded image data included in a top field and a bottom field of a B picture. The B-picture memory is controlled by a memory controller which independently controls a memory area storing the luminance data and another memory area storing the color-difference data in the memory. Preferably, the memory controller releases the memory area storing the luminance data included in one of the top and bottom fields that has been displayed.

Abstract: An image decoding apparatus, a semiconductor device, and a image decoding method are provided, capable of reducing the apparatus size and reducing the maximum value of current consumption, when simultaneously outputting a multi-channel digital images. A multiplexing processing portion 23 of the image decoding apparatus outputs a multiplexed data B1 obtained by time division multiplexing of the image data A1 to A3 stored in each memory 22 after output from the multi-channel image decoding portion 10 and a phase output signal C2 which indicates a phase of any one of image data among multiplexed image data A1 to A3. A synthesizing output processing portion 24 generates and outputs synthesized image data B2 for displaying more than two image data among image data A1 to A3 on one image screen. A selection output portion 25 outputs any one of the input multiplexed image data B1, the synthesized image data B2, and any one of image data A1 to A3 as a digital image data.