Patents by Inventor Taro Hasegawa
Taro Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10756507Abstract: A process of forming a semiconductor optical device is disclosed. The semiconductor optical device provides a waveguide structure accompanied with a heater for varying a temperature of the waveguide structure. The process includes steps of: (a) forming a striped mask on a semiconductor substrate; (b) selectively growing a dummy layer on the semiconductor substrate; (c) removing the patterned mask; (d) burying the dummy layer by a supplemental layer; (e) exposing a portion of the dummy layer by etching a portion of the supplemental layer; (f) and removing the dummy layer by immersing the dummy layer within a solution that shows an etching rate for the dummy layer enough faster than an etching rate for the supplemental layer and the substrate so as to leave a void in a region the dummy layer had existed.Type: GrantFiled: January 22, 2018Date of Patent: August 25, 2020Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Device Innovations, Inc.Inventors: Toshimitsu Kaneko, Takuya Fujii, Masami Ishiura, Taro Hasegawa, Toshiyuki Taguchi
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Patent number: 10330925Abstract: According to the present invention, a galvanometer scanner, comprising: an operation portion having a rotary shaft; an inner sliding member configured to rotatably support the rotary shaft; a reaction force absorbing portion, provided outside the rotary shaft via the inner sliding member, configured to replace a force acting against the operation portion with an angular acceleration; an outer sliding member configured to rotatably support the reaction force absorbing portion; and a fixed portion provided outside the reaction force absorbing portion via the outer sliding member, is provided.Type: GrantFiled: November 16, 2017Date of Patent: June 25, 2019Assignee: Sodick Co., Ltd.Inventors: Ichiro Araie, Mitsuru Murai, Taro Hasegawa
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Publication number: 20180212400Abstract: A process of forming a semiconductor optical device is disclosed. The semiconductor optical device provides a waveguide structure accompanied with a heater for varying a temperature of the waveguide structure. The process includes steps of: (a) forming a striped mask on a semiconductor substrate; (b) selectively growing a dummy layer on the semiconductor substrate; (c) removing the patterned mask; (d) burying the dummy layer by a supplemental layer; (e) exposing a portion of the dummy layer by etching a portion of the supplemental layer; (f) and removing the dummy layer by immersing the dummy layer within a solution that shows an etching rate for the dummy layer enough faster than an etching rate for the supplemental layer and the substrate so as to leave a void in a region the dummy layer had existed.Type: ApplicationFiled: January 22, 2018Publication date: July 26, 2018Inventors: Toshimitsu Kaneko, Takuya Fujii, Masami Ishiura, Taro Hasegawa, Toshiyuki Taguchi
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Patent number: 9985413Abstract: An optical semiconductor device comprises: a first insulating film provided on a semiconductor layer; a heater provided on the first insulating film; a second insulating film provided on the heater; and an electrode provided on the heater. The electrode extends on the second insulating film; the electrode is in contact with the heater; the second insulating film includes a first region on which the electrode is located; and a thickness of the first region of the second insulating film is greater than that of the first insulating film.Type: GrantFiled: September 29, 2014Date of Patent: May 29, 2018Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Taro Hasegawa, Toshiyuki Taguchi
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Publication number: 20180136459Abstract: According to the present invention, a galvanometer scanner, comprising: an operation portion having a rotary shaft; an inner sliding member configured to rotatably support the rotary shaft; a reaction force absorbing portion, provided outside the rotary shaft via the inner sliding member, configured to replace a force acting against the operation portion with an angular acceleration; an outer sliding member configured to rotatably support the reaction force absorbing portion; and a fixed portion provided outside the reaction force absorbing portion via the outer sliding member, is provided.Type: ApplicationFiled: November 16, 2017Publication date: May 17, 2018Applicant: Sodick Co., Ltd.Inventors: Ichiro ARAIE, Mitsuru MURAI, Taro HASEGAWA
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Patent number: 9890751Abstract: An air cleaner hose is provided. The air cleaner hose includes a bellows part and a low-rigidity part. The low-rigidity part is in a region between the bellows part and one end of the air cleaner hose. The low-rigidity part is included in a part of the air cleaner hose in a circumferential direction, wherein the low-rigidity part is configured to have a buckling deformation such that a buckling load of the low-rigidity part with respect to a compressive load in an axial direction of the air cleaner hose is smaller than a buckling load of a region other than the low-rigidity part with respect to the compressive load.Type: GrantFiled: December 14, 2015Date of Patent: February 13, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuji Matsubara, Taro Hasegawa, Shinya Makihara
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Publication number: 20160177889Abstract: An air cleaner hose is provided. The air cleaner hose includes a bellows part and a low-rigidity part. The low-rigidity part is in a region between the bellows part and one end of the air cleaner hose. The low-rigidity part is included in a part of the air cleaner hose in a circumferential direction, wherein the low-rigidity part is configured to have a buckling deformation such that a buckling load of the low-rigidity part with respect to a compressive load in an axial direction of the air cleaner hose is smaller than a buckling load of a region other than the low-rigidity part with respect to the compressive load.Type: ApplicationFiled: December 14, 2015Publication date: June 23, 2016Applicant: Toyota Jidosha Kabushiki KaishaInventors: Yuji MATSUBARA, Taro Hasegawa, Shinya Makihara
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Patent number: 9031111Abstract: A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.Type: GrantFiled: June 20, 2014Date of Patent: May 12, 2015Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Tatsuya Takeuchi, Taro Hasegawa
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Publication number: 20150092799Abstract: An optical semiconductor device comprises: a first insulating film provided on a semiconductor layer; a heater provided on the first insulating film; a second insulating film provided on the heater; and an electrode provided on the heater. The electrode extends on the second insulating film; the electrode is in contact with the heater; the second insulating film includes a first region on which the electrode is located; and a thickness of the first region of the second insulating film is greater than that of the first insulating film.Type: ApplicationFiled: September 29, 2014Publication date: April 2, 2015Inventors: Taro HASEGAWA, Toshiyuki TAGUCHI
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Publication number: 20140302628Abstract: A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.Type: ApplicationFiled: June 20, 2014Publication date: October 9, 2014Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Tatsuya Takeuchi, Taro Hasegawa
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Patent number: 8798110Abstract: A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.Type: GrantFiled: April 26, 2011Date of Patent: August 5, 2014Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Tatsuya Takeuchi, Taro Hasegawa
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Patent number: 8276489Abstract: A spindle apparatus includes a rotatable first spindle (5, 32) to which a tool can be attached. The first spindle is supported in a base with high precision using an air hydrostatic bearing. The spindle apparatus further includes a second spindle (6, 33) capable of rotation about an axis substantially aligned with the axis of the first spindle, first connection means for electrically connecting a base side and the second spindle, and second connection means for electrically connecting the first spindle and the second spindle. Electrical connection between the base side and the first spindle is carried out via the first and second connection means. The first connection means is, for example, a brush (15, 36). The second connection means has a degree of mechanical freedom and is, for example, a flexible electrical wire (17, 39) or a helical spring (51).Type: GrantFiled: February 27, 2007Date of Patent: October 2, 2012Assignee: Sodick Co., Ltd.Inventors: Ichiro Araie, Shuichi Kawada, Taro Hasegawa
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Publication number: 20110261855Abstract: A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.Type: ApplicationFiled: April 26, 2011Publication date: October 27, 2011Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventors: Tatsuya Takeuchi, Taro Hasegawa
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Patent number: 7919415Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.Type: GrantFiled: October 29, 2007Date of Patent: April 5, 2011Assignee: Fujitsu Quantum Devices LimitedInventors: Takayuki Watanabe, Tsutomu Michitsuta, Taro Hasegawa, Takuya Fujii
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Publication number: 20090133546Abstract: A spindle apparatus includes a rotatable first spindle (5, 32) to which a tool can be attached. The first spindle is supported in a base with high precision using an air hydrostatic bearing. The spindle apparatus further includes a second spindle (6, 33) capable of rotation about an axis substantially aligned with the axis of the first spindle, first connection means for electrically connecting a base side and the second spindle, and second connection means for electrically connecting the first spindle and the second spindle. Electrical connection between the base side and the first spindle is carried out via the first and second connection means. The first connection means is, for example, a brush (15, 36). The second connection means has a degree of mechanical freedom and is, for example, a flexible electrical wire (17, 39) or a helical spring (51).Type: ApplicationFiled: February 27, 2007Publication date: May 28, 2009Inventors: Ichiro Araie, Shuichi Kawada, Taro Hasegawa
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Publication number: 20080070419Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.Type: ApplicationFiled: October 29, 2007Publication date: March 20, 2008Applicant: FUJITSU QUANTUM DEVICES LIMITEDInventors: Takayuki Watanabe, Tsutomu Michitsuta, Taro Hasegawa, Takuya Fujii
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Patent number: 7303933Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.Type: GrantFiled: June 20, 2005Date of Patent: December 4, 2007Assignee: Fujitsu Quantum Devices LimitedInventors: Takayuki Watanabe, Tsutomu Michitsuta, Taro Hasegawa, Takuya Fujii
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Publication number: 20050245089Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.Type: ApplicationFiled: June 20, 2005Publication date: November 3, 2005Applicant: Fujitsu Quantum Devices LimitedInventors: Takayuki Watanabe, Tsutomu Michitsuta, Taro Hasegawa, Takuya Fujii
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Patent number: 6924162Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.Type: GrantFiled: February 14, 2002Date of Patent: August 2, 2005Assignee: Fujitsu Quantum Devices LimitedInventors: Takayuki Watanabe, Tsutomu Michitsuta, Taro Hasegawa, Takuya Fujii
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Patent number: 6789305Abstract: In a linear motor coil assembly (12), and a method for manufacturing the same, a plurality of coils (14) are arranged in a line in a direction of movement and have respective coil axes perpendicular to the direction of movement of the motor. A flat cooling tube (20) is arranged to meander inside the plurality of coils. The cooling tube has a cross section elongated in a direction parallel to the coil axes, and a plurality of clearance holes (25) through which coolant flows are formed inside the cooling tube. The cooling tube has interleaved folds at least equal in number to the number of coils. The coils being fitted into these folds. At the time of manufacture of the coil assembly, the coils are wound around cores that are divided for each coil, and the cores are inserted into the folds of the cooling tube.Type: GrantFiled: October 8, 2003Date of Patent: September 14, 2004Assignee: Sodick Co., Ltd.Inventors: Yoichi Seki, Taro Hasegawa