Abstract: A member for a semiconductor manufacturing apparatus includes: a ceramic plate that has a wafer placement surface at an upper surface thereof; a plug disposition hole that extends through the ceramic plate in an up-down direction and that has a truncated conical space whose upper opening is larger than a lower opening thereof; a truncated conical plug that is disposed in the plug disposition hole, that allows gas to flow in the up-down direction, and whose upper surface is larger than a lower surface thereof; an adhesive layer that is provided between the plug disposition hole and the truncated conical plug; an electrically conductive baseplate that is joined to a lower surface of the ceramic plate through a joint layer; and a gas supply path that is provided in the baseplate and the joint layer and that supplies gas to the truncated conical plug.

Abstract: A member for a semiconductor manufacturing apparatus includes a ceramic plate; a composite plate joined to a lower surface of the ceramic plate; a cooling plate formed of a metal material, disposed on a lower surface of the composite plate; a first fastener that fastens the composite plate and the cooling plate; a support plate that is formed of an insulating material and supports a lower surface of the cooling plate; and a second fastener that fastens the cooling plate and the support plate, wherein, when the ceramic plate is heated from room temperature to high temperature, a first layered body including the ceramic plate and the composite plate deforms such that a central portion of the first layered body is convex, and a second layered body including the cooling plate and the support plate deforms such that a central portion of the second layered body is convex.

Abstract: A wafer placement table includes an upper substrate; a lower substrate; a through hole extending through the lower substrate in an up-down direction; a plurality of projections provided in a dot pattern, for example, at an entirety of an upper surface of the lower substrate and being in contact with the lower surface of the upper substrate; a heat dissipation sheet having a projection insertion hole and being disposed between the upper substrate and the lower substrate; a screw hole provided, in the lower surface of the upper substrate, at a position facing the through hole; a screw member inserted from a lower surface of the lower substrate into the through hole and screwed into the screw hole.

Abstract: A wafer placement table includes an upper substrate; a lower substrate; a through hole extending through the lower substrate in an up-down direction; a plurality of projections provided in a dot pattern, for example, at an entirety of an upper surface of the lower substrate and being in contact with the lower surface of the upper substrate; a heat dissipation sheet having a projection insertion hole and being disposed between the upper substrate and the lower substrate; a screw hole provided, in the lower surface of the upper substrate, at a position facing the through hole; a screw member inserted from a lower surface of the lower substrate into the through hole and screwed into the screw hole; and a thermally conductive paste interposed, for example, between side surfaces of the projections and an inner peripheral surface of the projection insertion hole of the heat dissipation sheet.

Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .

Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .