Patents by Inventor Tarun Gupta
Tarun Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9716583Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.Type: GrantFiled: July 13, 2016Date of Patent: July 25, 2017Assignee: MACOM CONNECTIVITY SOLUTIONS, LLCInventors: Moshe Malkin, Tarun Gupta
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Publication number: 20160365970Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.Type: ApplicationFiled: July 13, 2016Publication date: December 15, 2016Inventors: Moshe Malkin, Tarun Gupta
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Patent number: 9485039Abstract: Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array.Type: GrantFiled: June 11, 2015Date of Patent: November 1, 2016Assignee: APPLIED MICRO CIRCUITS CORPORATIONInventors: Moshe Malkin, Tarun Gupta
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Patent number: 9397822Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.Type: GrantFiled: June 11, 2015Date of Patent: July 19, 2016Assignee: APPLIED MICRO CIRCUITS CORPORATIONInventors: Moshe Malkin, Tarun Gupta
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Patent number: 9325287Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port.Type: GrantFiled: January 24, 2014Date of Patent: April 26, 2016Assignee: APPLIED MICRO CIRCUITS CORPORATIONInventors: Nanda Govind Jayaraman, Tarun Gupta
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Publication number: 20150326376Abstract: Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.Type: ApplicationFiled: August 22, 2014Publication date: November 12, 2015Inventors: Dariush Dabiri, Tarun Gupta, Venkatesh Nagapudi
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Publication number: 20150326197Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor.Type: ApplicationFiled: January 24, 2014Publication date: November 12, 2015Applicant: APPLIED MICRO CIRCUITS CORPORATIONInventors: Nanda Govind Jayaraman, Tarun Gupta
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Publication number: 20150326379Abstract: Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds.Type: ApplicationFiled: February 13, 2014Publication date: November 12, 2015Applicant: APPLIED MICRO CIRCUITS CORPORATIONInventors: Dariush Dabiri, Tarun Gupta, Venkatesh Nagapudi
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Patent number: 9059723Abstract: Provided is a digital-to-analog converter configured to mitigate data dependent jitter of switch driver signals. The digital-to-analog converter is configured to produce data patterns of “0001000”. The digital-to-analog converter includes a digital portion that includes a digital data input component, an analog portion, and a conversion component. The conversion component includes a decoder configured to split a first data stream comprising a set of digital data into a first data sub-stream and a second data sub-stream, and a second data stream comprising another set of digital data into a third data sub-stream and a fourth data sub-stream. The conversion component also includes a first pair of drivers, a second pair of drivers, a third pair of drivers, and a fourth pair of drivers, wherein respective drivers of the first, second, third, and fourth pairs of drivers are configured to output respective data patterns comprising at least three consecutive identical bits.Type: GrantFiled: August 22, 2014Date of Patent: June 16, 2015Assignee: Applied Micro Circuits CorporationInventors: Ramesh Kumar Singh, Tarun Gupta
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Patent number: 8786319Abstract: A system and method have been provided for passively isolating a latch circuit. The method provides a latch having a first input, an output, and a reset port. The latch first input is selectively connected to a first reference voltage. While the latch first input is connected to the first reference voltage, the latch is reset. Subsequent to disconnecting the latch first input from the first reference voltage, a first node is selectively connecting to the latch first input. In response to selectively connecting the first node, a first analog signal is supplied to the latch first input. Subsequent to resetting the latch, the first analog signal is captured and the latch output supplies a digital signal responsive to the captured first analog signal.Type: GrantFiled: March 16, 2012Date of Patent: July 22, 2014Assignee: Applied Micro Circuits CorporationInventors: Dong Wang, Tarun Gupta
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Patent number: 8742849Abstract: A linear source follower amplifier is provided with a first metal-oxide semiconductor (MOS) field effect transistor (FET) having a gate to accept an ac input signal and a source to supply an ac output signal. A second MOS FET has a gate to accept the ac input signal, a source connected to the drain of the first MOS FET. A third MOS FET has a drain connected to the source of the first MOS FET, a gate connected to the drain of the second MOS FET, and a source connected to a first reference voltage. A fourth MOS FET has a drain and a gate connected to the drain of the second MOS FET and a source connected to the first reference voltage. A current source has an input connected to a second reference voltage, and an output connected to the drain of the first MOS FET.Type: GrantFiled: April 2, 2012Date of Patent: June 3, 2014Assignee: Applied Micro Circuits CorporationInventors: Tarun Gupta, Ramesh Kumar Singh
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Patent number: 8737278Abstract: A full-duplex wire-line transceiver is provided with echo cancellation line driver. The transceiver has an impedance matching network with a network interface, and a transmit interface to accept a differential transmit signal for transmission via the network. The impedance matching network has a receive interface to supply a differential receive signal accepted at the network interface, where the transmit interface is coupled to the receive interface. A hybrid circuit has an input to accept the differential receive signal combined with a coupled differential transmit signal, and input to accept a differential echo cancellation (EC) signal. The hybrid circuit has an output to supply the differential receive signal with the coupled differential transmit signal attenuated in response to the differential EC signal. A line driver uses an active current mirror to generate matched transmit and EC signals.Type: GrantFiled: November 17, 2011Date of Patent: May 27, 2014Assignee: Applied Micro Circuits CorporationInventors: Frank Yang, Tarun Gupta
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Patent number: 8239807Abstract: A method for generating a standard cell layout pattern for standard cell placement in an integrated circuit uses a congestion map. First, congestion zones are identified in a congestion map generated by an Electronic Design Automation (EDA) application. Next, routing tracks data corresponding to bounding boxes belonging to the congestion zones are used to calculate values of average vertical and horizontal congestion. Subsequently, a value of modified standard cell density is calculated based on the values of average vertical and horizontal congestion, and an unmodified standard cell density. The dimensions of a layout pattern unit are calculated using the value of the modified standard cell density and the width of standard cells. Various layout pattern units then are placed adjacent to one another to form a standard cell layout pattern.Type: GrantFiled: June 1, 2010Date of Patent: August 7, 2012Assignee: Freescale Semiconductor, IncInventors: Pankaj Arora, Tarun Gupta, Manoj Singh
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Publication number: 20110296366Abstract: A method for generating a standard cell layout pattern for standard cell placement in an integrated circuit uses a congestion map. First, congestion zones are identified in a congestion map generated by an Electronic Design Automation (EDA) application. Next, routing tracks data corresponding to bounding boxes belonging to the congestion zones are used to calculate values of average vertical and horizontal congestion. Subsequently, a value of modified standard cell density is calculated based on the values of average vertical and horizontal congestion, and an unmodified standard cell density. The dimensions of a layout pattern unit are calculated using the value of the modified standard cell density and the width of standard cells. Various layout pattern units then are placed adjacent to one another to form a standard cell layout pattern.Type: ApplicationFiled: June 1, 2010Publication date: December 1, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Pankaj Arora, Tarun Gupta, Manoj Singh