Abstract: Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.

Abstract: Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.

Abstract: Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.

Abstract: A method of making polycrystalline silicon (p-Si), including: depositing amorphous silicon to produce an amorphous silicon super-mesa; dehydrogenating the amorphous silicon; patterning the super-mesa to produce a patterned substrate; depositing a capping oxide layer on the amorphous silicon on the patterned substrate; heating the capped, patterned substrate to the crystallization temperature of the a-Si; and flash lamp annealing the patterned substrate with a xenon lamp to produce p-Si having at least one super-mesa, and the super-mesa having supersized grains. Also disclosed are p-Si articles and devices incorporating the articles, and an apparatus for making the p-Si articles.

Abstract: Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.

Abstract: A method of making polycrystalline silicon (p-Si), including: depositing amorphous silicon to produce an amorphous silicon super-mesa; dehydrogenating the amorphous silicon; patterning the super-mesa to produce a patterned substrate; depositing a capping oxide layer on the amorphous silicon on the patterned substrate; heating the capped, patterned substrate to the crystallization temperature of the a-Si; and flash lamp annealing the patterned substrate with a xenon lamp to produce p-Si having at least one super-mesa, and the super-mesa having supersized grains. Also disclosed are p-Si articles and devices incorporating the articles, and an apparatus for making the p-Si articles.