Abstract: A data communication device includes a host receive section for receiving incoming host data from a host device. The host receive section includes a plurality of host receive lanes. A host transmit section for transmitting outgoing host data to the host device includes a plurality of host transmit lanes and a host cross point section. A line receive section for receiving incoming line data from a line device includes a plurality of line receive lanes. A line transmit section for transmitting outing line data to the line device includes a plurality of line transmit lanes and a line cross point section. A link monitor section coupled to the host transmit section and the line receive section is configured to detect errors between the host transmit section and the line receive section.

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.

Abstract: A high speed interface for ancillary data is provided. The interface extracts ancillary data encoded in a serial digital data signal received over the serial digital data input; assembles a plurality of data packets, each packet comprising identification information identifying the data packet, length information identifying a length of the data packet, and value information representing a portion of the extracted ancillary data; sequentially encodes the plurality of data packets within a high-speed data stream; and transmits the high speed data stream via a high speed data output.

Abstract: A method for converting data received in either a Level A or Level B SMPTE 425M compliant format into either a Level B or a Level A compliant format, respectively, includes receiving and processing data in one of a Level A or a Level B SMPTE 425M compliant format. Inputting the received Level A formatted data into a storage device and reading out Level B formatted data at an output of the storage device, or inputting Level B formatted data into the storage device and reading out Level A formatted data at an output of the storage device. Back-end circuitry further processes the Level A formatted data when Level B formatted data is received or further processes the Level B formatted data when Level A formatted data is received. The storage device is operated as a line multiplexer to convert data in a Level B format to data in a Level A format and is operated as a line demultiplexer to convert data in a Level A format to data in a Level B format.

Abstract: A method for converting data received in either a Level A or Level B SMPTE 425M compliant format into either a Level B or a Level A compliant format, respectively, includes receiving and processing data in one of a Level A or a Level B SMPTE 425M compliant format. Inputting the received Level A formatted data into a storage device and reading out Level B formatted data at an output of the storage device, or inputting Level B formatted data into the storage device and reading out Level A formatted data at an output of the storage device. Back-end circuitry further processes the Level A formatted data when Level B formatted data is received or further processes the Level B formatted data when Level A formatted data is received. The storage device is operated as a line multiplexer to convert data in a Level B format to data in a Level A format and is operated as a line demultiplexer to convert data in a Level A format to data in a Level B format.

Abstract: A high-speed video serializer has an X bit parallel input bus and a Y bit parallel output bus, where X and Y are multiples of one another (e.g., 2). A multiplexer is connected between the input bus and the output bus and is operated such that a frequency of the signals on the output bus is a multiple of the frequency of the signals on the input bus. A circuit provides a clock signal substantially in sync with the signals on the output bus. A high speed video deserializer is also disclosed as are methods of operating the serializer and deserializer.