Abstract: A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. Such a communication device includes a processor configured to perform codeword builder functionality to generate information that undergoes error checking and correction (ECC) and/or forward error correction (FEC) coding. The processor intelligently selects packets from buffers to generate information blocks that undergo ECC and/or FEC coding and transmission and to meet certain latency constraints in conjunction with a predetermined period of time (e.g., a programmable threshold).

Abstract: A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. Such a communication device includes a processor configured to perform codeword builder functionality to generate information that undergoes error checking and correction (ECC) and/or forward error correction (FEC) coding. The processor intelligently selects packets from buffers to generate information blocks that undergo ECC and/or FEC coding and transmission and to meet certain latency constraints in conjunction with a predetermined period of time (e.g., a programmable threshold).

Abstract: Embodiments of a digital up-converter and an N-channel modulator are provided herein. The embodiments of the digital up-converter, in combination with the N-channel modulator, are capable of efficiently filling the spectrum of one or more RF signals with one or more types of information signals. For example, the digital up-converter can fill the spectrum of one or more RF signals with both broadcast and narrowcast video and data signals. In addition, the digital up-converter is capable of flexibly mapping the information signals to one or more channels of the one or more RF signals using a novel, three-level switching architecture.

Abstract: Embodiments of a digital up-converter and an N-channel modulator are provided herein. The embodiments of the digital up-converter, in combination with the N-channel modulator, are capable of efficiently filling the spectrum of one or more RF signals with one or more types of information signals. For example, the digital up-converter can fill the spectrum of one or more RF signals with both broadcast and narrowcast video and data signals. In addition, the digital up-converter is capable of flexibly mapping the information signals to one or more channels of the one or more RF signals using a novel, three-level switching architecture.

Abstract: Embodiments of a digital up-converter and an N-channel modulator are provided herein. The embodiments of the digital up-converter, in combination with the N-channel modulator, are capable of efficiently filling the spectrum of one or more RF signals with one or more types of information signals. For example, the digital up-converter can fill the spectrum of one or more RF signals with both broadcast and narrowcast video and data signals. In addition, the digital up-converter is capable of flexibly mapping the information signals to one or more channels of the one or more RF signals using a novel, three-level switching architecture.

Abstract: A system and method demodulate N QAM signals (N being a positive integer equal to or greater than 1) substantially simultaneously using, for example, one or two oscillators, regardless of how many QAM signals need to be demodulated.

Abstract: A network monitor includes means for monitoring downstream traffic from a cable modem termination system (CMTS) to a cable modem (CM), means for monitoring upstream traffic from the CM to the CMTS, and means for identifying a data format used by the CMTS and the CM for bi-directional communication.

Abstract: A system and method demodulate N QAM signals (N being a positive integer equal to or greater than 1) substantially simultaneously using, for example, one or two oscillators, regardless of how many QAM signals need to be demodulated.

Abstract: A network monitor includes means for monitoring downstream traffic from a cable modem termination system (CMTS) to a cable modem (CM), means for monitoring upstream traffic from the CM to the CMTS, and means for identifying a data format used by the CMTS and the CM for bi-directional communication.

Abstract: A DSP receiver for a fast turnaround modem, particularly suited for a half duplex fast turnaround modem which prevents destruction of communication channel related adaptive equalizer parameters upon loss of carrier. Upon detection of carrier loss, after sufficient time has been allowed for the last informational data bits to pass through the receiver's adaptive equalizer, the output of the equalizer's FIR filter delay line is looped back, via a multiplexer, to the input of the equalizer so that communications channel related samples are continuously provided to the equalizer to maintain the parameters at values based on the receiver's actual experience with data transmitted through the communications channel to which it is connected. A delay timer responsive to the loss of carrier signal will terminate updating of the adaptive equalizer parameters a predetermined time after loss of carrier. Alternately, detection of a standard end of data flag in the data stream will also terminate parameter update.

Abstract: An autocorrelator for FSK signals. An FSK signal, incoming on a telephone line is filtered by a bandpass filter (13) and sampled by an A/D converter (14). A sample clock (15) provides a fixed sampling frequency, FS. A first interpolating filter (20B) provides selectable delays which are non-integer multiples of 1/FS, and an integer delay (25) provides selectable delays which are integer multiples of 1/FS. The delayed signals are multiplied by a multiplier (26) and then filtered by a low pass filter (27) to provide a filtered autocorrelated signal. A second interpolating filter (20A) provides for reduced jitter in the baud timing by increasing the number of samples provided to the decision logic (23). The decision logic (23) provides the decoded data output.

Abstract: An improved circuit for providing automatic gain control (AGC) for incoming phase shift keyed (PSK) and quadrature amplitude modulated (QAM) signals. An absolute value circuit (193) and a comparator (195) provide a first error signal (197). An integrater (200,202) smoothes the first error signal (197) to provide a second error signal (201) to a variable-threshold threshold detector (204). The threshold (209) is initially set at a low value to allow the AGC circuit to quickly respond. A larger value is then used to reduce susceptibility to noise and provide for proper QAM operation. An error circuit (208,211,213) provides a non-linear response so that the gain variations will be small when the input signal (190) is large. This non-linear response further reduces the effects of noise on the AGC circuit.

Abstract: A data communications receiver for use in a modem. A fixed sample clock and a dominated tap tracking algorithm lock the local baud timing in the receiver to the baud timing in a remote transmitter. An interpolating filter provides a plurality of discrete delays. A filter control circuit inspects the tap coefficients of an adaptive equalizer to determine the location of and any movement of the dominant tap. The filter control circuit selects the rate of cycling through the discrete delays to compensate for any frequency difference between the local baud timing and the remote baud timing, and to prevent movement of the dominant tap. A baud detector circuit monitors the sample clock and the operating state of the filter control circuit to identify the end of a baud and detects and corrects for any frequency difference between the remote baud timing and the local baud timing by providing one additional sample or one less sample to the adaptive equalizer.

Abstract: A phase locked loop circuit which eliminates the phase difference between an incoming reference signal and a sampling signal by sampling the incoming reference signal to produce a sampled signal. The sign of the sampled signal at two sample points is compared to determine in which quadrant a predetermined one of these sample points is located. The phase adjustment to the sampling signal is dependent upon the quadrant in which this sample point is located and the magnitude of this sample point. A large phase difference produces a large phase adjustment so that this sample point is quickly locked onto the zero-crossing points of the incoming reference signal. A small phase difference produces a small phase adjustment and prevents jitter. The lock onto the zero-crossing point of the incoming reference signal minimizes the data error rate of the modem.

Abstract: An improved circuit for generating phase and amplitude modulated signals in a modem. A first circuit (161) generates a first signal (163) using a 1200 Hz carrier (160) and an input data stream (162). This signal (163) is generated at the rate of 7200 samples per second. The first signal (163) is then sampled by a sampler (164) at a 3600 Hz rate (165). The sampled signal (166) contains both a 1200 Hz signal and a 2400 Hz signal. A bandpass filter (43) selects a 1200 Hz or a 2400 Hz center frequency. The resulting output (44) is a selectable 1200 Hz or 2400 Hz signal which is generated using only the data sampling points necessary to generate the first, 1200 Hz signal (163).

Abstract: A modem with improved signal processing and handshaking capabilities as described. Two digital signal processors are used to perform independent, concurrent operations so that a faster execution rate is obtained and more precise calculations are made possible. The modem also uses an improved handshaking technique which allows the modem to maintain compatibility with existing 1200 and 2400 bps modems while allowing for negotiation for 4800 and 9600 bps communications. The modem also incorporates an improved baud clock recovery circuit which dynamically adjusts the actual sampling point in a manner dependent upon the difference between the actual sampling point and the optimal sampling point. This allows the actual sampling point to converge upon the desired sampling point at a high rate while minimizing jitter around the optimal sampling point.

Abstract: An improved V.22 bis 2400 bits per second (bps) handshake sequence detector. An incoming phase keyed (PSK) handshake sequence is autocorrelated using a frequency shift keyed (FSK) receiver (101). The autocorrelated signal is then filtered by a low pass filter (106). The autocorrelated, low pass filtered signal is then alternately fed, at a 1200 Hz rate, to two detectors (114,116). Each of the detectors (114,116) looks for one half of the handshake sequence. The output of each detector (114,116) is provided to an OR-gate (122). The 2400 bps handshake sequence is declared to be detected when either one or both of the detectors (114,116) detects its corresponding portion of the sequence.

Abstract: An improved baud clock recovery, synchronization and data sampling circuit for a modem. A CODEC (41) samples the incoming signal at a rate determined by the sample clock output of a presettable counter (236). The sampled signal is then squared (231) and bandpass filtered (232) to provide a recovered baud clock. A detector (233) signals the positive going zero-crossing points of the recovered baud clock. A lead/lag calculator (234) determines which of the signal samples is nearest the zero-crossing point. The calculator (234) then determines whether this and every subsequent 12th sampling point leads or lags the zero-crossing point by inspecting the sign of the recovered baud clock and adjusts the preset inputs of the counter (236) to cause the sample points to occur at the zero-crossing point.