Patents by Inventor Tat C. Choi

Tat C. Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9030155
    Abstract: Multi-mode charger device for charging portable devices and methods of charging portable devices are described. In an embodiment, a multi-mode charger device has mode blocks respectively associated with modes of operation which are coupled to a switch module. The switch module is for coupling a selected one of the mode blocks to a peripheral bus and to decouple the mode blocks remaining from the peripheral bus. A first mode of the modes of operation is a pass through mode. A second mode of the modes of operation is a first charging mode. A third mode of the modes of operation is a second charging mode. The first charging mode and the second charging mode are different from one another.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: May 12, 2015
    Assignee: Pericom Semiconductor Corporation
    Inventors: Xianxin Li, Hong-Leong Hong, Adbullah Raouf, Anna Tam, John Chi-Hung Hui, Tat C. Choi
  • Patent number: 8237414
    Abstract: Multi-mode charger device for charging portable devices and methods of charging portable devices are described. In an embodiment, a multi-mode charger device has mode blocks respectively associated with modes of operation which are coupled to a switch module. The switch module is for coupling a selected one of the mode blocks to a peripheral bus and to decouple the mode blocks remaining from the peripheral bus. A first mode of the modes of operation is a pass through mode. A second mode of the modes of operation is a first charging mode. A third mode of the modes of operation is a second charging mode. The first charging mode and the second charging mode are different from one another.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: August 7, 2012
    Assignee: Pericom Semiconductor Corporation
    Inventors: Xianxin Li, Hong-Leong Hong, Adbullah Raouf, Anna Tam, John Chi-Hung Hui, Tat C. Choi
  • Patent number: 8044711
    Abstract: A method and apparatus for clock signal noise shaping are described. Embodiments of a clock circuit include a filter coupled to receive an input clock signal and to provide an output clock signal. The filter filters noise of the input clock signal to shape the noise to provide the output clock signal. In a method for adjustment of phase noise, input clock signaling having the phase noise is obtained, and the input clock signal is filtered to adjust the phase noise to provide output clock signaling.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: October 25, 2011
    Assignee: Pericom Semiconductor Corporation
    Inventors: Michael Yimin Zhang, Tat C. Choi
  • Patent number: 5473342
    Abstract: A RAMDAC circuit drives a display device so as display multiple modes of color depth and display resolution in a single display frame without sacrificing resolution of the higher-resolution mode, and adjusts the output pixel rate to match that of the display mode being display on a pixel-by-pixel basis. The RAMDAC circuit switches between two graphics modes on-the-fly on a pixel-by-pixel basis in accordance with mode control bits stored in the pixel data. Furthermore, the RAMDAC circuit switches between two output pixel rates such that the amount of video memory used for any predefined screen area remains constant even though the output pixel rate and resolution are dynamically adjusted.
    Type: Grant
    Filed: October 19, 1993
    Date of Patent: December 5, 1995
    Assignee: Chrontel, Inc.
    Inventors: Lawrence T. Tse, Tat C. Choi, David C. Soo
  • Patent number: 4951112
    Abstract: A 4T static RAM cell (10) comprising a flip-flop with two pull-down transistors (18, 20) and two pass-gate transistors (12, 14) is fabaricated employing two separate gate oxide formations (74, 76) and associated separate polysilicon depositions (52a -b, 56). Two reduced area contacts (58, 60) connect to the nodes (26, 30) of the circuit (10). The reduced area butting contacts comprise vertically-disposed, doped polysilicon plugs (94), which intersect and electrically interconnect buried polysilicon layers (load poly 88, gate poly 52a) with doped silicon regions (80) in a bottom layer. Adding the processing steps of forming separate gate oxides for the pull-down and pass-gate transistors results in a smaller cell area and reduces the requirements of the contacts from three to two. Further, the separate gate oxidations permit independent optimization of the pull-down and pass-gate transistors.
    Type: Grant
    Filed: December 7, 1988
    Date of Patent: August 21, 1990
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tat C. Choi, Richard K. Klein, Craig S. Sander
  • Patent number: 4912540
    Abstract: A reduced area butting contact structure (10') is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a gate polysilicon. An anisotropic etch is then performed through all upper layers including any upper polysilicon layers which may be present, but stopping at the doped silicon region and any gate polysilicon layers present, to form a contact hole (26'). The contact hole is filled with a conductive plug (32) of a material such as tungsten or polysilicon and etched back. In either case, contact with all polysilicon layers present and the doped silicon region is made. In the anisotropic etching process, a two-step etch is employed.
    Type: Grant
    Filed: August 5, 1988
    Date of Patent: March 27, 1990
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Craig S. Sander, Richard K. Klein, Tat C. Choi