Abstract: A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

Abstract: A Quadrature-In, Quadrature-Out (QIQO) clock divider divides by an odd divisor, such as three. An IQ input clock has in-phase and quadrature differential signals. Four stages of dynamic logic are arranged into a loop, with each stage output being one of four IQ output signals that have 90-degree phase separations. Each stage output drives the gates of a p-channel charging transistor and an n-channel discharging transistor of a next stage. Two p-channel charging logic transistors are in series between the next stage output and the p-channel charging transistor, and two n-channel evaluation transistors are in series between the next stage output and the n-channel discharging transistor. Different pairs of the four IQ input clock signals are applied to their gates. When the prior stage output is low, the stage output is charged. When the prior stage output is high, the stage output discharge timing is determined by the IQ signals.

Abstract: A Phase-Locked Loop (PLL) has a multi-curve voltage-controlled oscillator (VCO) with a curve-select input that adjusts the capacitance within the VCO and thus the VCO gain. A calibration unit generates a curve-select value to the VCO. Coarse calibration selects a Center Curve CC value using binary search of the curve-select bits. During fine calibration, the number of pulses of the VCO output are counted and stored for all curves in a target window around the center curve. The stored pulse counts are compared to an ideal pulse count for a specified frequency, and the curve-select value for the closest-matching pulse count is applied to the VCO. The target window is much smaller than all possible curves, so calibration is performed only on a few curves, reducing calibration time. A switch before the VCO opens the loop for faster open-loop calibration. Pulses are counted digitally without expensive analog comparators.

Abstract: A two-point modulation Phase-Locked Loop (PLL) has a gain-adjustable voltage-controlled oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to a Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. A calibration unit divides the VCO output and counts pulses. During calibration, the data modulation signal is set to minimum and then maximum values and VCO output pulses counted. A count difference for the data modulation signal at maximum and minimum values is input to a Look-Up Table (LUT) to read out a gain calibration value. During normal operation mode, the gain calibration value from the LUT is applied to a second input of the DAC, which drives the VCO to adjust VCO gain. A switch before the VCO opens the loop for faster open-loop calibration.

Abstract: An Amplitude-Shifted-Keyed (ASK) modulator/transmitter has fall time enhanced by pulsing pull-up and pull-down enhancement switches on for a short period of time after a data transition. The enhancement switches draw energy from a coupling capacitor to more rapidly reduce an amplitude of the carrier wave being output. An input carrier wave is applied to gates of p-channel and n-channel current sources that drive the coupling capacitor. Gates of the n-channel and p-channel enhancement switches also receive the input carrier wave when data is high, but are disabled when data is low. Multiple p-channel and n-channel transistors may be used in parallel for each current source or enhancement switch. Each of the multiple transistors in parallel has a gate that is AND'ed with an index signal. The index signals are programmable and determine how many of the parallel transistors are enabled, thus determining the aggregate current.

Abstract: An envelope detector receives an input that is an Amplitude-Modulated (AM) or Amplitude-Shift-Keying (ASK) coded signal. Each channel has a sample switch and a diode that charge an internal sampling capacitor. A hold switch connects the internal sampling capacitor to a summing output capacitor or to a post-processing circuit. A reset switch discharges the internal sampling capacitor after each sample. Two or more channels may be time multiplexed to sample alternate cycles of the input, and then their outputs combined by the summing output capacitor or by the post-processing circuit. The diodes may be reversed to detect the negative envelope rather than the positive envelope. Clocks for the switches may be generated from the input, or may be from a separate clock source. Since the sampling window is open for a whole input cycle, the clock source is insensitive to phase error.