Abstract: A germanium-containing semiconductor device and a method for forming a germanium-containing semiconductor device are described. The method includes providing a germanium-containing substrate, depositing a silicon-containing interface layer on the germanium-containing substrate, depositing an aluminum-containing diffusion barrier layer on the silicon-containing interface layer, and depositing a high-k layer on the aluminum-containing diffusion barrier layer. The germanium-containing semiconductor device includes a germanium-containing substrate, a silicon-containing interface layer on the germanium-containing substrate, an aluminum-containing diffusion barrier layer on the silicon-containing interface layer, and a high-k layer on the aluminum-containing diffusion barrier layer.

Abstract: A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor.

Abstract: A method for forming a semiconductor device includes forming a graded silicon-germanium (SiGe) layer overlying a silicon substrate, a concentration of germanium increasing with a thickness of the graded silicon germanium layer. A first relaxed SiGe layer is formed over the graded SiGe layer, and a second relaxed SiGe layer overlying the first relaxed SiGe layer. The second relaxed SiGe layer has a lower conductivity than the first relaxed SiGe layer. The method also includes forming a field effect transistor having a trench extending into the second relaxed SiGe layer and a channel region that includes a layer of strained silicon to enable enhanced carrier mobility. A top conductor layer is formed overlying the second relaxed SiGe layer, and then the silicon substrate and the graded SiGe layer are removed. A bottom conductor layer is formed underlying the first relaxed SiGe layer.

Abstract: A method of forming a field effect transistor having a heavily doped p-type (110) semiconductor layer over a metal substrate starts with providing a heavily doped p-type (110) silicon layer, and forming a lightly doped p-type (110) silicon layer on the P heavily doped-type (110) silicon layer. The method also includes forming a p-channel MOSFET which has a channel region along a (110) crystalline plane in the lightly doped p-type (110) silicon layer to allow a current conduction in a <110> direction. The p-channel MOSFET also includes a gate dielectric layer having a high dielectric constant material lining the (110) crystalline plane. The method further includes forming a top conductor layer overlying the lightly doped p-type (110) silicon layer and a bottom conductor layer underlying the heavily doped p-type (110) silicon layer.

Abstract: A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor.

Abstract: A method of forming a field effect transistor having a heavily doped p-type (110) semiconductor layer over a metal substrate starts with providing a heavily doped p-type (110) silicon layer, and forming a lightly doped p-type (110) silicon layer on the P heavily doped-type (110) silicon layer. The method also includes forming a p-channel MOSFET which has a channel region along a (110) crystalline plane in the lightly doped p-type (110) silicon layer to allow a current conduction in a <110> direction. The p-channel MOSFET also includes a gate dielectric layer having a high dielectric constant material lining the (110) crystalline plane. The method further includes forming a top conductor layer overlying the lightly doped p-type (110) silicon layer and a bottom conductor layer underlying the heavily doped p-type (110) silicon layer.

Abstract: In certain embodiments, a thermoelectric device apparatus includes a plurality of laterally spaced-apart electrodes disposed upon a supporting structure, and at least one complementary pair of thermoelectric elements, each thermoelectric element coupling an electrode to a laterally adjacent electrode. Such a structure reduces the need for solder joints or other structures or mechanisms to attach multiple substrates, components, or assemblies together to form a thermoelectric device.

Abstract: A vertical, monolithic, thin-film thermoelectric device is described. Thermoelectric elements of opposing conductivity types may be coupled electrically in series and thermally in parallel by associated electrodes on a single substrate, reducing the need for mechanisms to attach multiple substrates or components. Phonon transport may be separated from electron transport in a thermoelectric element. A thermoelectric element may have a thickness less than an associated thermalization length. An insulating film between an electrode having a first temperature and an electrode having a second temperature may be a low-thermal conductivity material, a low-k, or ultra-low-k dielectric. Phonon thermal conductivity between a thermoelectric element and an electrode may be reduced without a significant reduction in electron thermal conductivity, as compared to other thermoelectric devices. A phonon conduction impeding material may be included in regions coupling an electrode to an associated thermoelectric element (e.g.

Abstract: A vertical, monolithic, thin-film thermoelectric device is described. Thermoelectric elements of opposing conductivity types may be coupled electrically in series and thermally in parallel by associated electrodes on a single substrate, reducing the need for mechanisms to attach multiple substrates or components. Phonon transport may be separated from electron transport in a thermoelectric element. A thermoelectric element may have a thickness less than an associated thermalization length. An insulating film between an electrode having a first temperature and an electrode having a second temperature may be a low-thermal conductivity material, a low-k, or ultra-low-k dielectric. Phonon thermal conductivity between a thermoelectric element and an electrode may be reduced without a significant reduction in electron thermal conductivity, as compared to other thermoelectric devices. A phonon conduction impeding material may be included in regions coupling an electrode to an associated thermoelectric element (e.g.

Abstract: A vertical, monolithic, thin-film thermoelectric device is described. Thermoelectric elements of opposing conductivity types may be coupled electrically in series and thermally in parallel by associated electrodes on a single substrate, reducing the need for mechanisms to attach multiple substrates or components. Phonon transport may be separated from electron transport in a thermoelectric element. A thermoelectric element may have a thickness less than an associated thermalization length. An insulating film between an electrode having a first temperature and an electrode having a second temperature may be a low-thermal conductivity material, a low-k, or ultra-low-k dielectric. Phonon thermal conductivity between a thermoelectric element and an electrode may be reduced without a significant reduction in electron thermal conductivity, as compared to other thermoelectric devices. A phonon conduction impeding material may be included in regions coupling an electrode to an associated thermoelectric element (e.g.

Abstract: A semiconductor device with dual gate electrodes and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric are formed over a first doped region. The metal/gate stack comprises a metal portion over the first gate dielectric and a first gate portion over the metal portion. A silicon gate and a second gate dielectric are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN.

Abstract: A semiconductor device with dual gate electrodes and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric are formed over a first doped region. The metal/gate stack comprises a metal portion over the first gate dielectric and a first gate portion over the metal portion. A silicon gate and a second gate dielectric are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN.