Patents by Inventor Tatsuaki Iwata
Tatsuaki Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11888990Abstract: An information processing device of one embodiment includes a first memory being volatile, a second memory being non-rewritable and nonvolatile, and a processor. A first program, a second program, and a digital signature for the second program are loaded into the first memory. A third program and a public key are stored in the second memory. Upon satisfaction of a certain condition during execution of the first program, the processor verifies the second program on the basis of the digital signature and the public key, in accordance with the third program. After finding a result of the verification as a pass, the processor analyzes the first program in accordance with the second program. The processor refrains from analyzing the first program after finding the result of the verification as a fail.Type: GrantFiled: August 26, 2020Date of Patent: January 30, 2024Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Yasuto Aramaki, Susumu Yasuda, Tatsuaki Iwata
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Patent number: 11856112Abstract: According to one embodiment, a server device includes a memory and a processor. The memory stores verification information. The processor accepts a request to transmit a certificate number, generates information in which identification information of one of storage devices from which data is to be erased, a public key, a secret key, and the certificate number are associated with one another, transmits the certificate number, performs verification using an authenticator transmitted by the one storage device and verification information, generates, based on a result of the verification, an erasure certificate that includes the identification information and the certificate number and is signed using the secret key, and transmits the erasure certificate.Type: GrantFiled: August 30, 2021Date of Patent: December 26, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Mika Fujishiro, Yasuto Aramaki, Tatsuaki Iwata, Hiromi Sakata, Taichiro Yamanaka, Daisuke Mito
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Publication number: 20220094557Abstract: According to one embodiment, a server device includes a memory and a processor. The memory stores verification information. The processor accepts a request to transmit a certificate number, generates information in which identification information of one of storage devices from which data is to be erased, a public key, a secret key, and the certificate number are associated with one another, transmits the certificate number, performs verification using an authenticator transmitted by the one storage device and verification information, generates, based on a result of the verification, an erasure certificate that includes the identification information and the certificate number and is signed using the secret key, and transmits the erasure certificate.Type: ApplicationFiled: August 30, 2021Publication date: March 24, 2022Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Mika FUJISHIRO, Yasuto ARAMAKI, Tatsuaki IWATA, Hiromi SAKATA, Taichiro YAMANAKA, Daisuke MITO
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Publication number: 20210281423Abstract: An information processing device of one embodiment includes a first memory being volatile, a second memory being non-rewritable and nonvolatile, and a processor. A first program, a second program, and a digital signature for the second program are loaded into the first memory. A third program and a public key are stored in the second memory. Upon satisfaction of a certain condition during execution of the first program, the processor verifies the second program on the basis of the digital signature and the public key, in accordance with the third program. After finding a result of the verification as a pass, the processor analyzes the first program in accordance with the second program. The processor refrains from analyzing the first program after finding the result of the verification as a fail.Type: ApplicationFiled: August 26, 2020Publication date: September 9, 2021Inventors: Yasuto ARAMAKI, Susumu YASUDA, Tatsuaki IWATA
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Patent number: 8184716Abstract: The image coding apparatus is provided to realize image coding with little calculation quantity and through rate distortion optimization thereby maintaining a favorable image quality. The image coding apparatus includes a processing unit that conducts frequency transform and quantization on a block in a predetermined manner for a plurality of coding modes, each mode having a different coding process, a cost calculating unit that calculates a predictive coded quantity and coding distortion in a coding mode using a result of the quantization conducted by the processing unit and a residue to obtain a cost regarding the coding mode, a minimum coding cost selecting unit that selects a minimum coding cost among the coding costs calculated for respective coding modes, and a coding unit that conducts coding on the blocks in a coding mode associated with the minimum coding cost selected by the minimum coding cost selecting unit.Type: GrantFiled: September 22, 2008Date of Patent: May 22, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tomoya Kodama, Atsushi Matsumura, Noboru Yamaguchi, Tatsuaki Iwata
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Patent number: 7502517Abstract: The image coding apparatus is provided to realize image coding with little calculation quantity and through rate distortion optimization thereby maintaining a favorable image quality. The image coding apparatus includes a processing unit that conducts frequency transform and quantization on a block in a predetermined manner for a plurality of coding modes, each mode having a different coding process, a cost calculating unit that calculates a predictive coded quantity and coding distortion in a coding mode using a result of the quantization conducted by the processing unit and a residue to obtain a cost regarding the coding mode, a minimum coding cost selecting unit that selects a minimum coding cost among the coding costs calculated for respective coding modes, and a coding unit that conducts coding on the blocks in a coding mode associated with the minimum coding cost selected by the minimum coding cost selecting unit.Type: GrantFiled: February 23, 2005Date of Patent: March 10, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tomoya Kodama, Atsushi Matsumura, Noboru Yamaguchi, Tatsuaki Iwata
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Publication number: 20090041122Abstract: The image coding apparatus is provided to realize image coding with little calculation quantity and through rate distortion optimization thereby maintaining a favorable image quality. The image coding apparatus includes a processing unit that conducts frequency transform and quantization on a block in a predetermined manner for a plurality of coding modes, each mode having a different coding process, a cost calculating unit that calculates a predictive coded quantity and coding distortion in a coding mode using a result of the quantization conducted by the processing unit and a residue to obtain a cost regarding the coding mode, a minimum coding cost selecting unit that selects a minimum coding cost among the coding costs calculated for respective coding modes, and a coding unit that conducts coding on the blocks in a coding mode associated with the minimum coding cost selected by the minimum coding cost selecting unit.Type: ApplicationFiled: September 22, 2008Publication date: February 12, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Tomoya Kodama, Atsushi Matsumura, Noboru Yamaguchi, Tatsuaki Iwata
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Publication number: 20080267596Abstract: According to one embodiment, in a recording medium in which a rewritable video manager and video objects are recorded, the video objects comprise video elementary streams defined in H.264, and the video manager includes information of the video objects having described therein a video object type in which a seamless flag and a seamless extension flag are described which show that the video objects are continuously and seamlessly reproduced for each of the video objects.Type: ApplicationFiled: June 25, 2008Publication date: October 30, 2008Inventors: Tatsuaki IWATA, Shinichiro Koto, Masahiro Nakashika, Tomoo Yamakage
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Publication number: 20070166008Abstract: In a recording medium in which a rewritable video manager and video objects are recorded, the video objects comprise video elementary streams defined in H.264, and the video manager includes information of the video objects having described therein a video object type in which a seamless flag and a seamless extension flag are described which show that the video objects are continuously and seamlessly reproduced for each of the video objects.Type: ApplicationFiled: January 8, 2007Publication date: July 19, 2007Inventors: Tatsuaki Iwata, Shinichiro Koto, Masahiro Nakashika, Tomoo Yamakage
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Publication number: 20060153299Abstract: A decoding section generates a decoded image and a coding parameter set from a first video coded video sequence. A coding parameter set conversion section first sets the coding structure for a pair of upper and lower macro blocks based on the coding structures of the corresponding macro blocks and converts the remaining parameters such as a motion vector based on the coding structure. A coding parameter set generation section generates coding parameters of an intraframe coding parameter, etc., a coding parameter set selection section selects an optimum parameter set, and a coding section performs recoding processing.Type: ApplicationFiled: January 3, 2006Publication date: July 13, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Tatsuaki Iwata, Shinichiro Koto, Wataru Asano, Tomoya Kodama
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Publication number: 20060061497Abstract: A bit rate of encoded moving picture data is converted in a system including a main processor, at least one sub processor and a main memory. In the main processor, a data acquisition unit acquires the encoded moving picture data from the main memory, a data analysis unit analyzes the encoded moving picture data, and an analysis data creation unit creates analysis data based on an analysis result. In the at least one sub processor, an analysis data acquisition unit acquires the analysis data, and a conversion processing unit converts the bit rate of the encoded moving picture data based on the analysis data.Type: ApplicationFiled: September 16, 2005Publication date: March 23, 2006Inventors: Atsushi Matsumura, Tomoya Kodama, Noboru Yamaguchi, Tatsuaki Iwata
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Publication number: 20050259752Abstract: An image processing apparatus includes a first image converter that performs a first image conversion on an original image and that obtains a converted image, a conversion information generator that generates conversion information determined based on a relationship between the original image and the converted image obtained by the first image converter, and a holding unit that holds the conversion information generated by the conversion information generator and the converted image subjected to the first image conversion while making the conversion information and the converted image correspond to each other.Type: ApplicationFiled: September 24, 2004Publication date: November 24, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuaki Iwata, Atsushi Matsumura, Noboru Yamaguchi, Tomoya Kodama
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Publication number: 20050213657Abstract: The image coding apparatus is provided to realize image coding with little calculation quantity and through rate distortion optimization thereby maintaining a favorable image quality. The image coding apparatus includes a processing unit that conducts frequency transform and quantization on a block in a predetermined manner for a plurality of coding modes, each mode having a different coding process, a cost calculating unit that calculates a predictive coded quantity and coding distortion in a coding mode using a result of the quantization conducted by the processing unit and a residue to obtain a cost regarding the coding mode, a minimum coding cost selecting unit that selects a minimum coding cost among the coding costs calculated for respective coding modes, and a coding unit that conducts coding on the blocks in a coding mode associated with the minimum coding cost selected by the minimum coding cost selecting unit.Type: ApplicationFiled: February 23, 2005Publication date: September 29, 2005Inventors: Tomoya Kodama, Atsushi Matsumura, Noboru Yamaguchi, Tatsuaki Iwata
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Publication number: 20050055710Abstract: A motion picture storage apparatus includes: a motion picture input unit which inputs motion picture data; a motion picture storage unit which sequentially stores the motion picture data; a condition storage unit which stores a condition related to a desirable scene previously set by a user; a motion picture analyzing unit configured to analyze the motion picture data stored in the motion picture storage unit to check whether a scene satisfying the condition is present, and configured to acquire specifying information of the scene satisfying the condition when the scene satisfying the condition is present; and an information notifying unit which notifies the specifying information to a device of the user.Type: ApplicationFiled: November 21, 2003Publication date: March 10, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hisashi Aoki, Tatsuaki Iwata, Noboru Yamaguchi, Tadaaki Masuda, Tomoya Kodama, Koichi Masukura, Atsushi Matsumura