Patents by Inventor Tatsuhiko ASAI
Tatsuhiko ASAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935813Abstract: A semiconductor device includes a semiconductor module having a wiring board, semiconductor assemblies that include a multilayer substrate on which semiconductor elements are mounted, and a sealing part; a cooler; and a heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and which is in contact with the bottom surfaces of the multilayer substrates. The heat conduction sheet has recesses corresponding to at least parts of the outer edges of second electrically conductive plates provided on the bottoms of the multilayer substrates.Type: GrantFiled: July 1, 2021Date of Patent: March 19, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Ryoichi Kato, Tatsuhiko Asai, Kento Shirata
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Patent number: 11581252Abstract: A semiconductor module includes at least two semiconductor elements connected in parallel; a control circuit board placed between the at least two semiconductor elements; a control terminal for external connection; a first wiring member that connects the control terminal and the control circuit board; and a second wiring member that connects a control electrode of one of the at least two semiconductor elements and the control circuit board, wherein the second wiring member is wire-bonded from the control electrode towards the control circuit board, and has a first end on the control electrode and a second end on the control circuit board, the first end having a cut end face facing upward normal to a surface of the control electrode and the second end having a cut end face facing sideways parallel to a surface of the control circuit board.Type: GrantFiled: March 1, 2021Date of Patent: February 14, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takafumi Yamada, Kohei Yamauchi, Tatsuhiko Asai, Hiromichi Gohara
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Publication number: 20220278039Abstract: Provided is a semiconductor module including: an insulating circuit board having a circuit pattern formed in one surface; a semiconductor chip placed in the insulating circuit board; and a wiring portion for electrically connecting the semiconductor chip and the circuit pattern. The wiring portion includes a chip connecting portion connected to the semiconductor chip. A surface of the chip connecting portion includes: a plurality of concave portions; and a flat portion disposed between two concave portions.Type: ApplicationFiled: May 17, 2022Publication date: September 1, 2022Inventors: Mai SAITO, Akihiko IWAYA, Yoko NAKAMURA, Tatsuhiko ASAI, Hiromichi GOHARA, Tsubasa WATAKABE, Narumi SATO
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Patent number: 11380599Abstract: There is provided a semiconductor module including: a base for semiconductor cooling; a stacked substrate provided above the base; a semiconductor chip provided above the stacked substrate; a coating layer provided on an upper surface of the semiconductor chip; and a sealing resin for sealing the semiconductor chip, in which the base is in contact with the sealing resin.Type: GrantFiled: February 24, 2020Date of Patent: July 5, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kohei Yamauchi, Tatsuhiko Asai
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Publication number: 20220183194Abstract: A semiconductor module includes a cooling device that includes: a ceiling plate; a side wall; a bottom plate; a plurality of pin fins having a polygonal shape and arranged in a matrix form in which one end of the respective pin fins is connected to a fin region having a rectangular shape; an inlet for a coolant at a first position adjacent to a part of one of long sides of the fin region, and an outlet for the coolant at a second position adjacent to a part of the other long side of the fin region. The matrix directions of the respective pin fins make an angle with a straight line connecting the first position and the second position, and a length of a segment of the straight line passing across the fin region is longer than a length of short sides of the fin region.Type: ApplicationFiled: February 24, 2022Publication date: June 9, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshihiro TATEISHI, Tatsuhiko ASAI, Takahiro KOYAMA, Hiromichi GOHARA
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Publication number: 20220005745Abstract: A semiconductor device includes a semiconductor module having a wiring board, semiconductor assemblies that include a multilayer substrate on which semiconductor elements are mounted, and a sealing part; a cooler; and a heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and which is in contact with the bottom surfaces of the multilayer substrates. The heat conduction sheet has recesses corresponding to at least parts of the outer edges of second electrically conductive plates provided on the bottoms of the multilayer substrates.Type: ApplicationFiled: July 1, 2021Publication date: January 6, 2022Inventors: Ryoichi KATO, Tatsuhiko ASAI, Kento SHIRATA
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Publication number: 20210287978Abstract: A semiconductor module includes at least two semiconductor elements connected in parallel; a control circuit board placed between the at least two semiconductor elements; a control terminal for external connection; a first wiring member that connects the control terminal and the control circuit board; and a second wiring member that connects a control electrode of one of the at least two semiconductor elements and the control circuit board, wherein the second wiring member is wire-bonded from the control electrode towards the control circuit board, and has a first end on the control electrode and a second end on the control circuit board, the first end having a cut end face facing upward normal to a surface of the control electrode and the second end having a cut end face facing sideways parallel to a surface of the control circuit board.Type: ApplicationFiled: March 1, 2021Publication date: September 16, 2021Applicant: Fuji Electric Co., Ltd.Inventors: Takafumi YAMADA, Kohei YAMAUCHI, Tatsuhiko ASAI, Hiromichi GOHARA
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Patent number: 10916491Abstract: A semiconductor module includes a semiconductor element having one and the other surface, a lead terminal connected electrically and thermally to the semiconductor element, a first solder which bonds the lead terminal and the one surface of the semiconductor element together, a circuit layer over which the semiconductor element is disposed and a second solder which bonds the other surface of the semiconductor element and the circuit layer together. The inequality (A/B)<1 holds, where A and B are the tensile strength of the first and second solder, respectively. As a result, even if the lead terminal which thermally expands because of heat generated by the semiconductor element expands or contracts toward the semiconductor element, a stress applied by the lead terminal is absorbed and relaxed by the first solder. This prevents damage to the surface electrode of the semiconductor element by suppressing the occurrence of cracks.Type: GrantFiled: September 4, 2018Date of Patent: February 9, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Ryoichi Kato, Kohei Yamauchi, Hiromichi Gohara, Tatsuhiko Asai
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Patent number: 10910324Abstract: A semiconductor device has a configuration in which a stacked assembly and a resin case are combined. The stacked assembly includes a semiconductor element, a stacked substrate on which the semiconductor element is mounted, and a metal substrate on which the stacked substrate is mounted. In the resin case, a notch groove is provided at a corner portion for reducing a stress. At least one of a width and a length of the notch groove is 2 mm or more.Type: GrantFiled: February 28, 2017Date of Patent: February 2, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tatsuhiko Asai, Katsumi Taniguchi
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Publication number: 20200402880Abstract: There is provided a semiconductor module including: a base for semiconductor cooling; a stacked substrate provided above the base; a semiconductor chip provided above the stacked substrate; a coating layer provided on an upper surface of the semiconductor chip; and a sealing resin for sealing the semiconductor chip, in which the base is in contact with the sealing resin.Type: ApplicationFiled: February 24, 2020Publication date: December 24, 2020Inventors: Kohei YAMAUCHI, Tatsuhiko ASAI
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Patent number: 10373919Abstract: A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and having an electrode pattern, a semiconductor element mounted on the stacked substrate, and a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern. The lead frame interconnection includes a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and second bonding portions. At least one of the first bonding portion and the second bonding portion is wider than the interconnect portion.Type: GrantFiled: August 1, 2017Date of Patent: August 6, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tatsuhiko Asai
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Patent number: 10256169Abstract: A highly-reliable semiconductor device has improved adhesion between a sealing material and a sealed metal member and/or a case member. In some implementations, the semiconductor device includes: a laminated substrate on which a semiconductor element is mounted; and a sealing material. In some implementations, the sealing material contains an epoxy base resin, a curing agent, and a phosphonic acid.Type: GrantFiled: February 28, 2017Date of Patent: April 9, 2019Assignee: Fuji Electric Co., Ltd.Inventors: Naoyuki Kanai, Tatsuhiko Asai
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Publication number: 20190088575Abstract: A semiconductor module includes a semiconductor element having one and the other surface, a lead terminal connected electrically and thermally to the semiconductor element, a first solder which bonds the lead terminal and the one surface of the semiconductor element together, a circuit layer over which the semiconductor element is disposed and a second solder which bonds the other surface of the semiconductor element and the circuit layer together. The inequality (A/B)<1 holds, where A and B are the tensile strength of the first and second solder, respectively. As a result, even if the lead terminal which thermally expands because of heat generated by the semiconductor element expands or contracts toward the semiconductor element, a stress applied by the lead terminal is absorbed and relaxed by the first solder. This prevents damage to the surface electrode of the semiconductor element by suppressing the occurrence of cracks.Type: ApplicationFiled: September 4, 2018Publication date: March 21, 2019Applicant: FUJI ELECTRIC CO., LTD.Inventors: Ryoichi Kato, Kohei Yamauchi, Hiromichi Gohara, Tatsuhiko Asai
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Patent number: 10128345Abstract: A semiconductor device including a semiconductor element, an upper-surface electrode provided on an upper surface of the semiconductor element, a plated layer provided on an upper surface of the upper-surface electrode, one or more gate runners penetrating the plated layer and provided to extend in a predetermined direction on the upper surface of the semiconductor element, and a metal connecting plate that is arranged above the plated layer and is electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion that is connected to a first end of the joint portion and extends in a direction away from the upper surface of the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, the rising portion and the gate runner do not overlap with each other.Type: GrantFiled: October 25, 2017Date of Patent: November 13, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Ryoichi Kato, Hiromichi Gohara, Takafumi Yamada, Kohei Yamauchi, Tatsuhiko Asai, Yoshitaka Nishimura, Akio Kitamura, Hajime Masubuchi, Souichi Yoshida
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Publication number: 20180166549Abstract: A semiconductor device including a semiconductor element, an upper-surface electrode provided on an upper surface of the semiconductor element, a plated layer provided on an upper surface of the upper-surface electrode, one or more gate runners penetrating the plated layer and provided to extend in a predetermined direction on the upper surface of the semiconductor element, and a metal connecting plate that is arranged above the plated layer and is electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion that is connected to a first end of the joint portion and extends in a direction away from the upper surface of the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, the rising portion and the gate runner do not overlap with each other.Type: ApplicationFiled: October 25, 2017Publication date: June 14, 2018Inventors: Ryoichi KATO, Hiromichi GOHARA, Takafumi YAMADA, Kohei YAMAUCHI, Tatsuhiko ASAI, Yoshitaka NISHIMURA, Akio KITAMURA, Hajime MASUBUCHI, Souichi YOSHIDA
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Publication number: 20180076149Abstract: A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and having an electrode pattern, a semiconductor element mounted on the stacked substrate, and a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern. The lead frame interconnection includes a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and second bonding portions. At least one of the first bonding portion and the second bonding portion is wider than the interconnect portion.Type: ApplicationFiled: August 1, 2017Publication date: March 15, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventor: Tatsuhiko ASAI
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Publication number: 20170278771Abstract: A highly-reliable semiconductor device has improved adhesion between a sealing material and a sealed metal member and/or a case member. In some implementations, the semiconductor device includes: a laminated substrate on which a semiconductor element is mounted; and a sealing material. In some implementations, the sealing material contains an epoxy base resin, a curing agent, and a phosphonic acid.Type: ApplicationFiled: February 28, 2017Publication date: September 28, 2017Applicant: Fuji Electric Co., Ltd.Inventors: Naoyuki Kanai, Tatsuhiko Asai
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Publication number: 20170271273Abstract: A semiconductor device has a configuration in which a stacked assembly and a resin case are combined. The stacked assembly includes a semiconductor element, a stacked substrate on which the semiconductor element is mounted, and a metal substrate on which the stacked substrate is mounted. In the resin case, a notch groove is provided at a corner portion for reducing a stress. At least one of a width and a length of the notch groove is 2 mm or more.Type: ApplicationFiled: February 28, 2017Publication date: September 21, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Tatsuhiko ASAI, Katsumi TANIGUCHI