Patents by Inventor Tatsuhiko Maruyama
Tatsuhiko Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230146002Abstract: According to the present embodiment, a power supply circuit includes a first transistor, a feedback voltage generation circuit, a first voltage generation circuit, and a protection circuit. The first transistor is connected between an input terminal and an output terminal. The feedback voltage generation circuit divides the output voltage to generate a feedback voltage. The first voltage generation circuit supplies a voltage to a first control terminal of the first transistor via a first node based on the feedback voltage and a reference voltage. The protection circuit outputs a voltage that makes the first transistor non-conducting or places the first transistor in a state where the first transistor has a predetermined high resistance value to the first control terminal, when the input voltage increases above a first threshold voltage within a predetermined time.Type: ApplicationFiled: August 26, 2022Publication date: May 11, 2023Inventors: Tatsuhiko MARUYAMA, Toyoaki UO
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Patent number: 11476802Abstract: A semiconductor device according to the present embodiment includes a plurality of switching elements and a plurality of variable capacitance elements. The switching elements are switching elements connected in series between a first control terminal and a second control terminal and plural types of capacitance control signals can be supplied to the first control terminal and the second control terminal. The variable capacitance elements have capacitance control terminals connected to corresponding one ends of the switching elements, respectively.Type: GrantFiled: August 27, 2021Date of Patent: October 18, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Tatsuhiko Maruyama
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Publication number: 20210391827Abstract: A semiconductor device according to the present embodiment includes a plurality of switching elements and a plurality of variable capacitance elements. The switching elements are switching elements connected in series between a first control terminal and a second control terminal and plural types of capacitance control signals can be supplied to the first control terminal and the second control terminal. The variable capacitance elements have capacitance control terminals connected to corresponding one ends of the switching elements, respectively.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Inventor: Tatsuhiko Maruyama
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Publication number: 20210297044Abstract: A semiconductor device according to the present embodiment includes a plurality of switching elements and a plurality of variable capacitance elements. The switching elements are switching elements connected in series between a first control terminal and a second control terminal and plural types of capacitance control signals can be supplied to the first control terminal and the second control terminal. The variable capacitance elements have capacitance control terminals connected to corresponding one ends of the switching elements, respectively.Type: ApplicationFiled: August 31, 2020Publication date: September 23, 2021Inventor: Tatsuhiko Maruyama
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Patent number: 11128257Abstract: A semiconductor device according to the present embodiment includes a plurality of switching elements and a plurality of variable capacitance elements. The switching elements are switching elements connected in series between a first control terminal and a second control terminal and plural types of capacitance control signals can be supplied to the first control terminal and the second control terminal. The variable capacitance elements have capacitance control terminals connected to corresponding one ends of the switching elements, respectively.Type: GrantFiled: August 31, 2020Date of Patent: September 21, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Tatsuhiko Maruyama
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Patent number: 10256726Abstract: A voltage conversion apparatus includes an output unit connected to an input voltage to output an output voltage according to a control signal. A comparator compares a reference voltage to a feedback voltage corresponding to the output voltage and outputs a comparison signal. A delay circuit outputs a delayed signal obtained by delaying either a rising timing or a falling timing of the comparison signal. The delay circuit varies a delay time of the delayed signal on basis of a modulating signal. A control circuit is configured to output the control signal to the output unit. The control signal is based on the delayed signal. The control circuit controls the output unit such that a frequency of the output voltage is tuned to a predetermined value set according to the modulating signal.Type: GrantFiled: August 28, 2017Date of Patent: April 9, 2019Assignee: Kabushiki Kaisha ToshibaInventor: Tatsuhiko Maruyama
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Publication number: 20190094896Abstract: According to an embodiment of the present invention, a power supply device includes a switching circuit, a detection circuit, a first comparator, a current source circuit, and a delay circuit. The switching circuit performs switching control of a power supply voltage. The detection circuit detects an output voltage from the switching circuit. The first comparator compares the voltage detected by the detection circuit with a first reference voltage which is set in advance. The current source circuit outputs a bias current which has correlation with the power supply voltage. The delay circuit receives the bias current from the current source circuit, and outputs, to the switching circuit, a delay time which corresponds to an increase time of the output voltage, by using the bias current in accordance with the result of comparison performed by the first comparator.Type: ApplicationFiled: March 16, 2018Publication date: March 28, 2019Inventor: Tatsuhiko Maruyama
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Patent number: 10241531Abstract: According to an embodiment of the present invention, a power supply device includes a switching circuit, a detection circuit, a first comparator, a current source circuit, and a delay circuit. The switching circuit performs switching control of a power supply voltage. The detection circuit detects an output voltage from the switching circuit. The first comparator compares the voltage detected by the detection circuit with a first reference voltage which is set in advance. The current source circuit outputs a bias current which has correlation with the power supply voltage. The delay circuit receives the bias current from the current source circuit, and outputs, to the switching circuit, a delay time which corresponds to an increase time of the output voltage, by using the bias current in accordance with the result of comparison performed by the first comparator.Type: GrantFiled: March 16, 2018Date of Patent: March 26, 2019Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Tatsuhiko Maruyama
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Publication number: 20180248483Abstract: A voltage conversion apparatus includes an output unit connected to an input voltage to output an output voltage according to a control signal. A comparator compares a reference voltage to a feedback voltage corresponding to the output voltage and outputs a comparison signal. A delay circuit outputs a delayed signal obtained by delaying either a rising timing or a falling timing of the comparison signal. The delay circuit varies a delay time of the delayed signal on basis of a modulating signal. A control circuit is configured to output the control signal to the output unit. The control signal is based on the delayed signal. The control circuit controls the output unit such that a frequency of the output voltage is tuned to a predetermined value set according to the modulating signal.Type: ApplicationFiled: August 28, 2017Publication date: August 30, 2018Inventor: Tatsuhiko MARUYAMA
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Publication number: 20150349759Abstract: A level shift circuit includes a first pair of transistors of the first conductive type (M1, M4) with sources coupled to a pair of input nodes (in, inB) and gates coupled to the first power supply (GND) in common; a second pair of transistors of the second conductive type (M2, M5) with drains coupled to the drains of the first pair of the transistors and the gates coupled to the first power supply in common; a third pair of transistors of the second conductive type (M3, M6) with cross-coupled gates and drains coupled to the sources of the second pair of transistors and the sources coupled to the second power supply (V2) in common; and a pair of capacitative elements (C1, C2) with one ends coupled to the pair of input nodes and the other ends coupled to the drains of the third pair of transistors.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Noriaki MATSUNO, Tatsuhiko MARUYAMA
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Patent number: 9136832Abstract: A level shift circuit includes a first pair of transistors of the first conductive type (M1, M4) with sources coupled to a pair of input nodes (in, inB) and gates coupled to the first power supply (GND) in common; a second pair of transistors of the second conductive type (M2, M5) with drains coupled to the drains of the first pair of the transistors and the gates coupled to the first power supply in common; a third pair of transistors of the second conductive type (M3, M6) with cross-coupled gates and drains coupled to the sources of the second pair of transistors and the sources coupled to the second power supply (V2) in common; and a pair of capacitative elements (C1, C2) with one ends coupled to the pair of input nodes and the other ends coupled to the drains of the third pair of transistors.Type: GrantFiled: January 29, 2013Date of Patent: September 15, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Noriaki Matsuno, Tatsuhiko Maruyama
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Patent number: 8629709Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.Type: GrantFiled: July 1, 2011Date of Patent: January 14, 2014Assignee: Renesas Electronics CorporationInventors: Tomoyuki Iraha, Tatsuhiko Maruyama
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Publication number: 20120001676Abstract: A switch circuit device includes a switch circuitry and a driver circuitry. The switch circuitry switches an electrical connection between first and second terminals between the on-state and the off-state in response to a set of control signals. The driver circuitry is configured to generate the control signals and includes an N-latch circuit and a leakage current suppression circuitry. The N-latch circuit selectively outputs lower one of two input voltages fed thereto as one of the control signals. The leakage current suppression circuitry suppresses the leakage current through the N-latch circuit.Type: ApplicationFiled: July 1, 2011Publication date: January 5, 2012Inventors: Tomoyuki IRAHA, Tatsuhiko Maruyama
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Publication number: 20090325525Abstract: Disclosed is a receiver so adapted that even it receives a signal having the same communication frequency and frequency band as its own, restart of a receive-signal processor is inhibited for a fixed period of time if the receive signal is not a desired signal. The result is a reduction in power consumption. The receiver includes a start circuit for detecting a radio-frequency signal and outputting a start signal if a level of the detected radio-frequency signal is no less than a fixed level, and a receive-signal processor for receiving the start signal and starting a demodulating operation for demodulating the radio-frequency signal.Type: ApplicationFiled: June 25, 2009Publication date: December 31, 2009Applicant: NEC Electronics CorporationInventor: Tatsuhiko MARUYAMA
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Patent number: 7456692Abstract: A gain variable amplifier according to an embodiment of the present invention includes: an amplifier circuit amplifying an input signal with a variable gain; and a gain control circuit controlling the gain of the amplifier circuit based on a gain control signal, in which the amplifier circuit includes: an amplifying element amplifying the input signal; an output element series-connected with the amplifying element and outputting a signal amplified with the amplifying element; and a bias circuit changing a potential at a node between the output element and the amplifying element based on the gain control of the gain control circuit.Type: GrantFiled: January 30, 2006Date of Patent: November 25, 2008Assignee: NEC Electronics CorporationInventors: Tatsuhiko Maruyama, Naohiro Matsui
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Publication number: 20080101260Abstract: A parent terminal collects remaining battery capacities of terminals (steps S201-S202, step S212) and monitors data transmission/reception amounts (step S203). The parent terminal calculates remaining battery times of the terminals, which are estimated assuming that each terminal becomes a parent terminal, from a change in the remaining battery capacities and the data transmission/reception amounts (step S208). Based on the calculation result, the parent terminal selects a terminal that maximizes the total of the remaining battery times of all terminals (average of remaining battery times of the terminals) as a parent terminal (step S209).Type: ApplicationFiled: October 30, 2007Publication date: May 1, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Tatsuhiko Maruyama
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Publication number: 20060170497Abstract: A gain variable amplifier according to an embodiment of the present invention includes: an amplifier circuit amplifying an input signal with a variable gain; and a gain control circuit controlling the gain of the amplifier circuit based on a gain control signal, in which the amplifier circuit includes: an amplifying element amplifying the input signal; an output element series-connected with the amplifying element and outputting a signal amplified with the amplifying element; and a bias circuit changing a potential at a node between the output element and the amplifying element based on the gain control of the gain control circuit.Type: ApplicationFiled: January 30, 2006Publication date: August 3, 2006Applicant: NEC COMPOUND SEMICONDUCTOR DEVICES, LTD.Inventors: Tatsuhiko Maruyama, Naohiro Matsui