Patents by Inventor Tatsuhiko Nagatani

Tatsuhiko Nagatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High voltage breakdown isolation semiconductor device and manufacturing process for making the device
    Patent number: 6596575
    Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer. Thus, a high breakdown voltage semiconductor device and a manufacturing process therefor is provided, which includes a low breakdown voltage element region and a high breakdown voltage element region, and a high breakdown isolation region separates a high breakdown voltage region without impairing the characteristics of an element formed on the low breakdown voltage element region.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: July 22, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuhiko Nagatani, Tomohide Terashima
  • High voltage breakdown isolation semiconductor device and manufacturing process for making the device
    Publication number: 20020089028
    Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer.
    Type: Application
    Filed: March 15, 2002
    Publication date: July 11, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tatsuhiko Nagatani, Tomohide Terashima
  • High voltage breakdown isolation semiconductor device and manufacturing process for making the device
    Patent number: 6376891
    Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer. Thus, a high breakdown voltage semiconductor device and a manufacturing process therefor is provided, which includes a low breakdown voltage element region and a high breakdown voltage element region, and a high breakdown isolation region separates a high breakdown voltage region without impairing the characteristics of an element formed on the low breakdown voltage element region.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: April 23, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuhiko Nagatani, Tomohide Terashima