Patents by Inventor Tatsuhiko Negishi

Tatsuhiko Negishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150126218
    Abstract: A system includes a plurality of information processing apparatuses, a case including a plurality of stages each configured to accommodate information processing apparatuses in a row, and a controller. The controller specifies, for each of the plurality of information processing apparatuses, a first fixed antenna among fixed antennas fixed to predetermined positions within the case or adjacent information processing apparatuses adjacent to the each information processing apparatus by causing the each information processing apparatus to conduct a wireless communication using the fixed antennas or antennas provided for the adjacent information processing apparatuses. The controller estimates a position of the each information processing apparatus within the case, based on the specified adjacent information apparatuses or the specified first fixed antenna.
    Type: Application
    Filed: October 14, 2014
    Publication date: May 7, 2015
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuhiko NEGISHI
  • Patent number: 8880972
    Abstract: A serial transmission apparatus, which transmits data through a serial communication line, includes a transmission unit configured to transmit data stored in a transmission data buffer to a transmission destination apparatus, a time-out detector configured to detect a time out when a response to the transmitted data from the transmission destination apparatus is not received within a specified period of time, a recovery state detector configured to detect a recovery state representing that the serial communication line is in a link recovery process, and a retransmission request unit configured to request the transmission unit to transmit again the data which has been stored in the transmission data buffer when the time-out detector detects the time-out or when the recovery state detector detects the recovery state of the serial communication line.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 4, 2014
    Assignee: Fujitsu Limited
    Inventors: Shogo Ogami, Kenji Shirase, Tatsuhiko Negishi
  • Patent number: 8671230
    Abstract: A data transfer device includes a storage controller that stores received response data in a buffer with respect to each piece of identification information included in the response data when receiving the response data from a first device, the response data being transferred from the first device in response to a transfer request transferred from a second device, a counting unit that counts a number of pieces of the response data stored in the buffer by the storage controller with respect to each piece of the identification information, and a determination unit that determines whether the number counted by the counting unit reaches a specified value preliminarily set with respect to each piece of the identification information.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Limited
    Inventors: Tatsuhiko Negishi, Kenji Shirase
  • Publication number: 20140064300
    Abstract: A data transfer apparatus includes a received-packet storage unit that is capable of storing received packets and retrieving the stored packets in an order different from the order in which these packets were received. The data transfer apparatus retrieves a packet from the received-packet storage unit in accordance with a request from a transfer-destination apparatus. When a packet initially received from a source apparatus from among the packets stored in the received-packet storage unit is retrieved, the data transfer apparatus transmits to the source apparatus a credit updated value that is proportional to the size of data that can be stored in the received-packet storage unit.
    Type: Application
    Filed: August 7, 2013
    Publication date: March 6, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tatsuhiko NEGISHI, Kenji SHIRASE
  • Publication number: 20120246263
    Abstract: A data transfer apparatus which transfers data sent from a first apparatus to a second apparatus, the data transfer apparatus including a first storage unit to store first data sent from the first apparatus, a second storage unit to store management information which manages a transmission state of transmission of the first data stored by the first storage unit to the second apparatus, a determination unit to dynamically determine a size of second data to be transferred to the second apparatus, in accordance with the transmission state, and a transmission unit to generate and transmit, to the second apparatus, the second data of the determined size which includes one or more pieces of the first data.
    Type: Application
    Filed: January 19, 2012
    Publication date: September 27, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tatsuhiko NEGISHI, Kenji SHIRASE, Syougo OGAMI
  • Publication number: 20120102293
    Abstract: A transmission device includes a plurality of memory units storing requests for processing information stored in a memory. Moreover, when a request from a first device is received, the transmission device analyzes the received request to specify an address range including a memory address storing data to be subjected to the requested processing. The transmission device stores requests in different memory units for each address range. Moreover, the transmission device determines for each memory unit whether the stored requests are being executed by a second device. The transmission device transmits a request which is stored in a memory unit and which is determined to be not being executed, to the second device.
    Type: Application
    Filed: August 1, 2011
    Publication date: April 26, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tatsuhiko NEGISHI, Kenji Shirase, Shogo Ogami
  • Publication number: 20120093211
    Abstract: A serial transmission apparatus, which transmits data through a serial communication line, includes a transmission unit configured to transmit data stored in a transmission data buffer to a transmission destination apparatus, a time-out detector configured to detect a time out when a response to the transmitted data from the transmission destination apparatus is not received within a specified period of time, a recovery state detector configured to detect a recovery state representing that the serial communication line is in a link recovery process, and a retransmission request unit configured to request the transmission unit to transmit again the data which has been stored in the transmission data buffer when the time-out detector detects the time-out or when the recovery state detector detects the recovery state of the serial communication line.
    Type: Application
    Filed: October 11, 2011
    Publication date: April 19, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Shogo OGAMI, Kenji SHIRASE, Tatsuhiko NEGISHI
  • Publication number: 20120096195
    Abstract: A data transfer device includes a storage controller that stores received response data in a buffer with respect to each piece of identification information included in the response data when receiving the response data from a first device, the response data being transferred from the first device in response to a transfer request transferred from a second device, a counting unit that counts a number of pieces of the response data stored in the buffer by the storage controller with respect to each piece of the identification information, and a determination unit that determines whether the number counted by the counting unit reaches a specified value preliminarily set with respect to each piece of the identification information.
    Type: Application
    Filed: September 6, 2011
    Publication date: April 19, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tatsuhiko NEGISHI, Kenji SHIRASE
  • Publication number: 20100083206
    Abstract: A clock signal providing circuit designing method for designing a clock signal providing circuit includes grouping circuit elements into a plurality of circuit groups each including a plurality of circuit elements, calculating an evaluation index value for each of the plurality of circuit groups and summing up calculated evaluation index values to obtain a first sum total, exchanging or moving provisionally at least one circuit element between the plurality of circuit groups, calculating an evaluation index value for each of the plurality of circuit groups and summing up calculated evaluation index values to obtain a second sum total, determining whether the second sum total decreases from the first sum total, fixing the circuit element provisionally exchanged or moved when the second sum total decreases from the first sum total and cancelling the circuit element provisionally exchanged or moved when the second sum total increases from the first sum total.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuhiko Negishi