Abstract: A reception device according to an embodiment in a system that performs wireless communication while switching a frequency channel includes a channel selecting unit, a generation unit, and a determination unit. The channel selecting unit converts a received signal of the frequency channel into a channel signal of an intermediate frequency. The generation unit generates a received channel number in a predetermined scheme. The determination unit determines whether or not to save a signal used for azimuth estimation in a storage unit from the channel signal.

Abstract: A wireless communication apparatus includes a transmission unit to transmit a communication control signal on each wireless communication channel in a plurality of wireless communication channels and an interference detection unit to detect interference on each wireless communication channel in the plurality of the wireless communication channels. A control unit controls the transmission unit to stop transmitting the communication control signal on any wireless communication channel in the plurality of wireless communications on which interference is detected by the interference detection unit.

Abstract: A wireless communication apparatus includes a transmission unit to transmit a communication control signal on each wireless communication channel in a plurality of wireless communication channels and an interference detection unit to detect interference on each wireless communication channel in the plurality of the wireless communication channels. A control unit controls the transmission unit to stop transmitting the communication control signal on any wireless communication channel in the plurality of wireless communications on which interference is detected by the interference detection unit.

Abstract: A clock frequency error detecting device includes a system storage portion which stores a synchronization system based on at least one of several types of frame synchronization signals included in a received signal in which a frame synchronization signal in each frame includes a part obtained by shifting of a frame synchronization signal of another frame by a symbol by using a predetermined rule; a pattern matching portion which performs pattern matching between the received signal and the synchronization system; a symbol counter which outputs a symbol number; a timing detection portion which detects the frame synchronization signal of each frame based on a pattern matching processing result and to output the symbol number at the detection timing; and a frequency error detection portion which detects a change of the symbol number and to detect a clock frequency error of the symbol period based on the detection.

Abstract: A receiving apparatus receives a digital modulation signal. The receiving apparatus has a receiving part for down-converting the digital modulation signal to a baseband signal and to obtain channel estimates, a channel estimation part for estimating a multi-path channel, a first replica generation part for generating a first replica, based on the channel estimates obtained by the channel estimation part, a first replica removal part for removing the first replica from a target frame in the baseband signal, a nulling part for forcefully nulling he baseband signal for at least a portion of the time period where an inter-frame interference occurs due to a delay wave having a delay time longer than the known signal, and a cyclic-addition part for performing cyclic-addition between a front side portion and a rear side portion in the target frame, including the portion nulled by the nulling part.

Abstract: Embodiments are provided: a known signal extraction circuit a distributing arrangement circuit which distributes a known signal in a fixed section; a frequency conversion circuit which causes the distributed output to be a frequency-domain signal; a delay detection circuit which determines an amount of phase variation between adjacent frequency components in the frequency-domain signal; a distributing arrangement circuit which distributes a signal of the same sequence as the known signal described above in a fixed section; a frequency conversion circuit which causes the distributed output to be a frequency-domain signal; a delay detection circuit which determines an amount of phase variation between adjacent frequency components in the frequency-domain signal; a correlation operation circuit which obtains a correlation value between two delay detection outputs; and a peak detection circuit which detects one or more high power peaks among the correlation values and obtain frequency difference from a reference

Abstract: The channel estimator includes a plurality of correlating sections configured to calculate a plurality of time correlation values between the signal and a plurality of known pattern signals having different code lengths, an analyzing section configured to output a control signal representing a selected period for extracting a preferable correlation output from the output from each of the plurality of correlating sections, and a delay profile generating section configured to output a delay profile obtained by adaptively selecting or combining parts of the outputs from the plurality of correlating sections based on the output from the analyzing section.

Abstract: A clock frequency error detecting device includes a system storage portion which stores a synchronization system based on at least one of several types of frame synchronization signals included in a received signal in which a frame synchronization signal in each frame includes a part obtained by shifting of a frame synchronization signal of another frame by a symbol by using a predetermined rule; a pattern matching portion which performs pattern matching between the received signal and the synchronization system; a symbol counter which outputs a symbol number; a timing detection portion which detects the frame synchronization signal of each frame based on a pattern matching processing result and to output the symbol number at the detection timing; and a frequency error detection portion which detects a change of the symbol number and to detect a clock frequency error of the symbol period based on the detection.

Abstract: A receiving apparatus receives a digital modulation signal. The receiving apparatus has a receiving part for down-converting the digital modulation signal to a baseband signal and to obtain channel estimates, a channel estimation part for estimating a multi-path channel, a first replica generation part for generating a first replica, based on the channel estimates obtained by the channel estimation part, a first replica removal part for removing the first replica from a target frame in the baseband signal, a nulling part for forcefully nulling he baseband signal for at least a portion of the time period where an inter-frame interference occurs due to a delay wave having a delay time longer than the known signal, and a cyclic-addition part for performing cyclic-addition between a front side portion and a rear side portion in the target frame, including the portion nulled by the nulling part.

Abstract: Embodiments are provided: a known signal extraction circuit a distributing arrangement circuit which distributes a known signal in a fixed section; a frequency conversion circuit which causes the distributed output to be a frequency-domain signal; a delay detection circuit which determines an amount of phase variation between adjacent frequency components in the frequency-domain signal; a distributing arrangement circuit which distributes a signal of the same sequence as the known signal described above in a fixed section; a frequency conversion circuit which causes the distributed output to be a frequency-domain signal; a delay detection circuit which determines an amount of phase variation between adjacent frequency components in the frequency-domain signal; a correlation operation circuit which obtains a correlation value between two delay detection outputs; and a peak detection circuit which detects one or more high power peaks among the correlation values and obtain frequency difference from a reference

Abstract: A frequency error detecting circuit includes: an oscillator; a frequency converting unit for a received signal on the basis of the oscillation output and output the received signal; a time-to-frequency converting unit configured to convert the output of the frequency converting unit into a frequency domain signal; a frequency shift determining unit configured to determine presence or absence of a frequency shift between an output frequency of the frequency converting unit and a predetermined carrier frequency; and a control unit configured to repeat frequency conversion processing and time-to-frequency conversion processing while controlling an oscillation frequency of the oscillator on the basis of a determination result of the frequency shift determining unit and cause the output frequency of the frequency converting unit to converge on a predetermined value to thereby detect a frequency error between the frequency of the received signal and the predetermined carrier frequency.

Abstract: According to an embodiment, a channel estimator includes a channel response estimation section configured to estimate a channel response by correlation processing between a received signal and a known pattern signal; a path power calculation section configured to measure power of each path within an output of the channel response estimation section; a noise power calculation section configured to measure noise power from the output of the channel response estimation section; a path determination section configured to determine paths to be preserved by using the path power outputted from the path power calculation section and the noise power outputted from the noise power calculation section; and a noise removal section configured to remove values in time domain excepting the paths determined at the path determination section, from the output of the channel response estimation section.

Abstract: The channel estimator includes a plurality of correlating sections configured to calculate a plurality of time correlation values between the signal and a plurality of known pattern signals having different code lengths, an analyzing section configured to output a control signal representing a selected period for extracting a preferable correlation output from the output from each of the plurality of correlating sections, and a delay profile generating section configured to output a delay profile obtained by adaptively selecting or combining parts of the outputs from the plurality of correlating sections based on the output from the analyzing section.

Abstract: A channel estimator includes: a delay time estimation section configured to estimate a delay time of a received signal; an FFT parameter determination section configured to determine an FFT window position and an FFT size according to the estimated delay time; a first and a second FFT sections configured to transform the received signal and a known pattern signal, respectively, to the frequency domain based on the FFT window position and the FFT size that are determined; a channel response calculation section configured to perform division processing to divide the output of the first FFT section by the output of the second FFT section; and an IFFT section configured to apply IFFT to the output of the channel response calculation section based on the determined FFT size, and the delay time estimation section estimates a delay time based on the output of the IFFT section.

Abstract: A frame number detecting device includes: a symbol counter that receives a received signal including frames each of which is formed of a predetermined number of symbols, and outputs a count value as a symbol number for each of the symbols by incrementing the count value by one every time one symbol is inputted, each of the frames including a frame synchronization signal including a part obtained by shifting a frame synchronization signal of a different frame on a symbol-by-symbol basis according to a predetermined rule; a sequence storage that stores a synchronization sequence based on at least one of the frame synchronization signals included in the received signal, and a pattern matching unit that performs pattern matching between the synchronization sequence stored in the sequence storage and the received signal.

Abstract: A frequency error detecting circuit includes: an oscillator; a frequency converting unit for a received signal on the basis of the oscillation output and output the received signal; a time-to-frequency converting unit configured to convert the output of the frequency converting unit into a frequency domain signal; a frequency shift determining unit configured to determine presence or absence of a frequency shift between an output frequency of the frequency converting unit and a predetermined carrier frequency; and a control unit configured to repeat frequency conversion processing and time-to-frequency conversion processing while controlling an oscillation frequency of the oscillator on the basis of a determination result of the frequency shift determining unit and cause the output frequency of the frequency converting unit to converge on a predetermined value to thereby detect a frequency error between the frequency of the received signal and the predetermined carrier frequency.