Abstract: The invention provides a method for improving image stitching accuracy and a device for implementing the same, which apply to the multi-camera system for wide-angle image generation. Lens distortion causes mismatches of the features in the overlapping region of the images captured by the multi-camera system. As a result, the mismatches on the stitched wide-angle image are visible. The method and device for improving image stitching accuracy correct the lens distortion before stitching the images captured by the multi-camera system, so that the features in the overlapping region are matched and a seamless wide-angle image is generated by the stitching engine.

Abstract: The invention discloses an optimized video stitching method, comprising: inputting predefined pattern images; proceeding with a transformation which combines planar and cylindrical transformation; proceeding with a merging calculation which combines linear difference merging and alpha blending calculation; and proceeding with a horizontal stitching processing by putting the processed images horizontally together into one seamless wide-angle image. The optimized video stitching method according to the invention further comprises a camera position calibration flow comprising: finding a planar matrix by using predefined pattern images; proceeding with a planar transformation of image; proceeding with an image registration by using a block matching method to find out the stitching points on the planar surface; and proceeding with a cylindrical transformation by transforming the stitching points from the planar surface to cylindrical surface.

Abstract: The invention provides a method for improving image stitching accuracy and a device for implementing the same, which apply to the multi-camera system for wide-angle image generation. Lens distortion causes mismatches of the features in the overlapping region of the images captured by the multi-camera system. As a result, the mismatches on the stitched wide-angle image are visible. The method and device for improving image stitching accuracy correct the lens distortion before stitching the images captured by the multi-camera system, so that the features in the overlapping region are matched and a seamless wide-angle image is generated by the stitching engine.

Abstract: The present invention provides a extracting and correcting method for a wide-angle image which can be a still image or a video stream. The method is able to display the extracted image without distortion. The correction method of the present invention is performed to map sections of the image to a plane with respect to their respective viewing angles. The present invention is adapted to progressively move the view angle and repeat the steps of extracting and correcting, thereby producing the panning effect without distortion.

Abstract: The invention discloses an optimized video stitching method, comprising: inputting predefined pattern images; proceeding with a transformation which combines planar and cylindrical transformation; proceeding with a merging calculation which combines linear difference merging and alpha blending calculation; and proceeding with a horizontal stitching processing by putting the processed images horizontally together into one seamless wide-angle image. The optimized video stitching method according to the invention further comprises a camera position calibration flow comprising: finding a planar matrix by using predefined pattern images; proceeding with a planar transformation of image; proceeding with an image registration by using a block matching method to find out the stitching points on the planar surface; and proceeding with a cylindrical transformation by transforming the stitching points from the planar surface to cylindrical surface.

Abstract: The present invention aims to simplify stitching algorithm which generates horizontal panoramic image. The image pickup device of the present invention comprises a plurality of lenses and positioning means. Said positioning means positions each lens so that the FOV (Field Of View) intersection points of all lenses are aligned in vertical direction. Accordingly, the horizontal parallax does not exist in the image picked up by the camera system and the stitching point remains the same for the objects at different distances.

Abstract: A processing circuit capable of realizing an operation including a logarithm of 2 operation with a small scale circuit configuration, wherein a priority encoder and a shaft circuit normalize g data, a table outputs &mgr;=“log2({1, qm})−qm” corresponding to a mantissa qm, another shift circuit shifts data obtained by bit coupling a data maxe comprised by only an integer part and a &mgr; data toward the MSB by L, another shift circuit shifts data obtained by bit coupling an exponent qe and the mantissa qm toward the MSB by L, an adder circuit adds −&dgr;2, −&ggr;2, and {K, 3′b0, 10}, and a clamp circuit clamps the result of addition to a predetermined number of bits.

Abstract: A division circuit which can shorten a critical path for division and can perform the division at a high speed, provided with a 1's complement processor for outputting a complement of 1 of a divisor when the divisor is negative; an adder for adding “1” to the output from the complement processor and making the result of addition an absolute value; a priority encoder for calculating a logarithmic value comprised of an integer value of a logarithm of 2 of the value output from the 1's complement processor, a shift processor for shifting the absolute value in accordance with the logarithmic value, making the shift processing value a mantissa when the MSB of the shift processing value is “1”, and making the shift processing value with an MSB replaced by “1” the mantissa when the MSB of the shift processing value is “0”, and a subtractor for determining the shift amount in response to the MSB of the shift processing value of the shift processor.

Abstract: An encoder capable of making a processing time shorter, wherein the position of a first “1” bit seen from the MSB of digital data is output as a first bit encoded data and the second “1” bit is output as the second bit encoded data. A predetermined calculation is performed in parallel on the upper 8 bits of the digital data in the valid detector, the priority encoder, and the first valid bit mask unit, while a predetermined calculation is performed in parallel on the lower 8 bits in another priority encoder and another first valid bit mask unit.