Patents by Inventor Tatsuo Chijimatsu

Tatsuo Chijimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230053433
    Abstract: A semiconductor device includes, above a substrate, a first layer with, on both sides in a direction, first regions; a second layer above the first layer with, on both sides in the direction, second regions above the first regions; a third layer, third regions, a fourth layer, and fourth regions, corresponding to the first layer, first regions, second layer, and second regions, respectively, the third layer being side by side with the first layer in another direction, the fourth layer being side by side with the second layer in the other direction; first and second gate electrodes above the first and second layers and the third and fourth layers, and having gate insulating films between these gate electrodes and these layers; and an insulating wall extending in the direction with both side surfaces contacted by the first and second layers and the third and fourth layers, respectively.
    Type: Application
    Filed: November 7, 2022
    Publication date: February 23, 2023
    Inventors: Haruhiko SERIZAWA, Tatsuo CHIJIMATSU
  • Patent number: 7818709
    Abstract: Circuit-pattern-data correction method and semiconductor-device manufacturing method which prevent excessive correction from being made when model-based proximity-effect correction (OPC) is applied to a corrected circuit pattern, the excessive correction being caused by a step (difference in level) close to a circuit-pattern corner in the corrected circuit pattern, and the step being produced when rule-base OPC is applied. The rule-based OPC is applied to input design data in step S1; a step close to a circuit-pattern corner, produced by the rule-based OPC is detected in step S2; the step is removed in step S3; and the model-based OPC is applied and exposure data is generated in step S4.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: October 19, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Atsushi Sagisaka, Tatsuo Chijimatsu
  • Publication number: 20070220477
    Abstract: Circuit-pattern-data correction method and semiconductor-device manufacturing method which prevent excessive correction from being made when model-based proximity-effect correction (OPC) is applied to a corrected circuit pattern, the excessive correction being caused by a step (difference in level) close to a circuit-pattern corner in the corrected circuit pattern, and the step being produced when rule-base OPC is applied. The rule-based OPC is applied to input design data in step S1; a step close to a circuit-pattern corner, produced by the rule-based OPC is detected in step S2; the step is removed in step S3; and the model-based OPC is applied and exposure data is generated in step S4.
    Type: Application
    Filed: September 5, 2006
    Publication date: September 20, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi Sagisaka, Tatsuo Chijimatsu
  • Patent number: 7199426
    Abstract: The nonvolatile semiconductor memory device comprises a channel region formed in a semiconductor substrate, a gate electrode formed over the channel region with a charge retaining insulating film interposed therebetween, a first pair of source/drain regions arranged in a first direction with the channel region formed therebetween, and a second pair of source/drain regions arranged in a second direction intersecting the first direction with the channel region formed therebetween. The channel region and the gate electrode are common between a first memory cell transistor including the first pair of source/drain regions and a second memory cell transistor including the second pair of source/drain regions.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: April 3, 2007
    Assignee: Fujitsu Limited
    Inventors: Jusuke Ogura, Hiroyuki Ogawa, Tatsuo Chijimatsu
  • Publication number: 20060081915
    Abstract: The nonvolatile semiconductor memory device comprises a channel region formed in a semiconductor substrate, a gate electrode formed over the channel region with a charge retaining insulating film interposed therebetween, a first pair of source/drain regions arranged in a first direction with the channel region formed therebetween, and a second pair of source/drain regions arranged in a second direction intersecting the first direction with the channel region formed therebetween. The channel region and the gate electrode are common between a first memory cell transistor including the first pair of source/drain regions and a second memory cell transistor including the second pair of source/drain regions.
    Type: Application
    Filed: March 10, 2005
    Publication date: April 20, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Jusuke Ogura, Hiroyuki Ogawa, Tatsuo Chijimatsu
  • Patent number: 6033134
    Abstract: In the production of semiconductor devices, a pattern-wise exposed resist coating is developed with a developer to form a resist pattern corresponding to the pattern of exposure radiation on an article to be fabricated. The development being carried out with a developer consisting of one or more organic solvents, in at least two stages and in each stage of the development, the development is interrupted when a substantial permeation of the developer of a surface portion of the pattern-forming area of the resist pattern in which the resist pattern remains is completed, and the developed resist coating is dried between this stage and the following development stages. The development of the exposed resist coating is carried out by using a developing apparatus which comprises at least one set of developer-supplying system and rinsing solution-supplying system, and a conveyor means for guiding the article carrying the resist coating.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: March 7, 2000
    Assignee: Fujitsu Limited
    Inventors: Takashi Maruyama, Tatsuo Chijimatsu, Koichi Kobayashi, Keiko Yano, Hiroyuki Kanata
  • Patent number: 5783367
    Abstract: In the production of semiconductor devices, a pattern-wise exposed resist coating is developed with a developer to form a resist pattern corresponding to the pattern of exposure radiation on an article to be fabricated. The development being carried out with a developer consisting of one or more organic solvents, in at least two stages and in each stage of the development, the development is interrupted when a substantial permeation of the developer of a surface portion of the pattern-forming area of the resist pattern in which the resist pattern remains is completed, and the developed resist coating is dried between this stage and the following development stages. The development of the exposed resist coating is carried out by using a developing apparatus which comprises at least one set of developer-supplying system and rinsing solution-supplying system, and a conveyor means for guiding the article carrying the resist coating.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: July 21, 1998
    Assignee: Fujitsu Limited
    Inventors: Takashi Maruyama, Tatsuo Chijimatsu, Koichi Kobayashi, Keiko Yano, Hiroyuki Kanata