Patents by Inventor Tatsuo Gou

Tatsuo Gou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect structure of semiconductor integrated circuit, and design method and device therefor
    Patent number: 7913221
    Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Hirofumi Miyashita, Chie Kabuo, Nobuyuki Iwauchi, Yoichi Matsumura, Fumihiro Kimura, Tatsuo Gou, Yukiji Hashimoto
  • Method for designing semiconductor integrated circuits having air gaps.
    Patent number: 7698671
    Abstract: Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: April 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Tsutomu Fujii, Hirofumi Miyashita, Hiromasa Fukazawa, Tatsuo Gou, Takuya Yasui
  • METHOD AND PROGRAM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD AND PROGRAM FOR SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD AND PROGRAM FOR CALCULATING WIRING PARASITIC CAPACITANCE
    Publication number: 20080120583
    Abstract: Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 22, 2008
    Inventors: Tsutomu Fujii, Hirofumi Miyashita, Hiromasa Fukazawa, Tatsuo Gou, Takuya Yasui
  • Interconnect structure of semiconductor integrated circuit, and design method and device therefor
    Publication number: 20080097641
    Abstract: A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
    Type: Application
    Filed: October 19, 2007
    Publication date: April 24, 2008
    Inventors: Hirofumi Miyashita, Chie Kabuo, Nobuyuki Iwauchi, Yoichi Matsumura, Fumihiro Kimura, Tatsuo Gou, Yukiji Hashimoto