Patents by Inventor Tatsuo Shinbashi
Tatsuo Shinbashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11262936Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.Type: GrantFiled: July 27, 2016Date of Patent: March 1, 2022Assignee: SONY CORPORATIONInventors: Ken Ishii, Hiroyuki Iwaki, Kenichi Nakanishi, Yasushi Fujinami, Tatsuo Shinbashi
-
Patent number: 11029881Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.Type: GrantFiled: April 17, 2017Date of Patent: June 8, 2021Assignee: SONY CORPORATIONInventors: Ken Ishii, Hiroyuki Iwaki, Kenichi Nakanishi, Yasushi Fujinami, Tatsuo Shinbashi
-
Publication number: 20200310681Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.Type: ApplicationFiled: April 17, 2017Publication date: October 1, 2020Inventors: KEN ISHII, HIROYUKI IWAKI, KENICHI NAKANISHI, YASUSHI FUJINAMI, TATSUO SHINBASHI
-
Patent number: 10635528Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.Type: GrantFiled: May 20, 2015Date of Patent: April 28, 2020Assignee: SONY CORPORATIONInventors: Tatsuo Shinbashi, Lui Sakai, Ryoji Ikegaya
-
Patent number: 10545804Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.Type: GrantFiled: July 22, 2015Date of Patent: January 28, 2020Assignee: Sony CorporationInventors: Tatsuo Shinbashi, Keiichi Tsutsui, Hideaki Okubo, Lui Sakai, Kenichi Nakanishi, Yasushi Fujinami
-
Patent number: 10481971Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.Type: GrantFiled: April 15, 2016Date of Patent: November 19, 2019Assignee: Sony CorporationInventors: Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Hiroyuki Iwaki, Ken Ishii, Hideaki Okubo
-
Patent number: 10338984Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.Type: GrantFiled: July 9, 2015Date of Patent: July 2, 2019Assignee: SONY CORPORATIONInventors: Yasushi Fujinami, Kenichi Nakanishi, Tsunenori Shiimoto, Tetsuya Yamamoto, Tatsuo Shinbashi, Hideaki Okubo, Haruhiko Terada, Ken Ishii, Hiroyuki Iwaki, Matatoshi Honjo
-
Publication number: 20190056884Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.Type: ApplicationFiled: July 27, 2016Publication date: February 21, 2019Inventors: KEN ISHII, HIROYUKI IWAKI, KENICHI NAKANISHI, YASUSHI FUJINAMI, TATSUO SHINBASHI
-
Patent number: 10177878Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.Type: GrantFiled: January 12, 2017Date of Patent: January 8, 2019Assignee: SONY CORPORATIONInventors: Kazuhisa Funamoto, Tatsuo Shinbashi, Tatsuya Sugioka, Kenichi Maruko, Naohiro Koshisaka, Hiroo Takahashi
-
Publication number: 20180232178Abstract: An access speed when a memory controller accesses a memory is improved. Each time any one of two different types of commands is input, a holding unit holds the input command. A priority mode switching unit switches a priority command which should have priority out of the two commands from one of the two commands to the other. A command processing unit preferentially extracts priority commands sequentially from the holding unit, and then sequentially extracts commands which are not the priority commands from the holding unit.Type: ApplicationFiled: June 15, 2016Publication date: August 16, 2018Inventors: Hiroyuki Iwaki, Ken Ishii, Yasushi Fujinami, Kennichi Nakanishi, Tatsuo Shinbashi
-
Publication number: 20180143871Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.Type: ApplicationFiled: April 15, 2016Publication date: May 24, 2018Inventors: Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Hiroyuki Iwaki, Ken Ishii, Hideaki Okubo
-
Publication number: 20170293513Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.Type: ApplicationFiled: July 22, 2015Publication date: October 12, 2017Inventors: Tatsuo Shinbashi, Keiichi Tsutsui, Hideaki Okubo, Lui Sakai, Kenichi Nakanishi, Yasushi Fujinami
-
Publication number: 20170255502Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.Type: ApplicationFiled: July 9, 2015Publication date: September 7, 2017Inventors: YASUSHI FUJINAMI, KENICHI NAKANISHI, TSUNENORI SHIIMOTO, TETSUYA YAMAMOTO, TATSUO SHINBASHI, HIDEAKI OKUBO, HARUHIKO TERADA, KEN ISHII, HIROYUKI IWAKI, MATATOSHI HONJO
-
Publication number: 20170147433Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.Type: ApplicationFiled: May 20, 2015Publication date: May 25, 2017Inventors: TATSUO SHINBASHI, LUI SAKAI, RYOJI IKEGAYA
-
Publication number: 20170126361Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.Type: ApplicationFiled: January 12, 2017Publication date: May 4, 2017Inventors: Kazuhisa Funamoto, Tatsuo Shinbashi, Tatsuya Sugioka, Kenichi Maruko, Naohiro Koshisaka, Hiroo Takahashi
-
Patent number: 9608668Abstract: Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a predetermined condition, the received word having a plurality of symbols, the determination process including determining if a determination-target symbol has an error or not, and detecting an error position, the error position being a position of the symbol having an error; changing, by a determination-target changing unit, the position of the determination-target symbol of the received word every time the determination process is executed; detecting, by an undetected-position detector, if the predetermined condition is satisfied, the error position of the symbol, for which the determination process is not executed, based on a relation between the error position and a variable generated from the received word; and correcting, by an error corrector, an error at the error position detected by the error-position detector and the undetected-position detector.Type: GrantFiled: October 30, 2014Date of Patent: March 28, 2017Assignee: Sony CorporationInventors: Ryoji Ikegaya, Tatsuo Shinbashi, Yasushi Fujinami
-
Patent number: 9565424Abstract: There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.Type: GrantFiled: November 30, 2012Date of Patent: February 7, 2017Assignee: SONY CORPORATIONInventors: Kazuhisa Funamoto, Tatsuo Shinbashi, Tatsuya Sugioka, Kenichi Maruko, Naohiro Koshisaka, Hiroo Takahashi
-
Patent number: 9417956Abstract: An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data.Type: GrantFiled: January 14, 2014Date of Patent: August 16, 2016Assignee: Sony CorporationInventors: Lui Sakai, Ryoji Ikegaya, Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Makiko Yamamoto
-
Patent number: 9361952Abstract: Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data.Type: GrantFiled: February 28, 2013Date of Patent: June 7, 2016Assignee: SONY CORPORATIONInventors: Kenichi Nakanishi, Keiichi Tsutsui, Yasushi Fujinami, Naohiro Adachi, Hideaki Okubo, Ken Ishii, Tatsuo Shinbashi
-
Patent number: 9280455Abstract: Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.Type: GrantFiled: July 19, 2013Date of Patent: March 8, 2016Assignee: SONY CORPORATIONInventors: Naohiro Adachi, Keiichi Tsutsui, Ken Ishii, Hideaki Okubo, Kenichi Nakanishi, Yasushi Fujinami, Tatsuo Shinbashi, Lui Sakai, Ryoji Ikegaya