Patents by Inventor Tatsuo Suemasu

Tatsuo Suemasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190327829
    Abstract: A stretchable board includes: a substrate having a stretching property; and a conductor portion provided on the substrate, wherein the conductor portion comprises: conductor wires intersecting with each other; and an opening surrounded by the conductor wires.
    Type: Application
    Filed: February 6, 2017
    Publication date: October 24, 2019
    Applicant: Fujikura Ltd.
    Inventors: Shingo OGURA, Tatsuo SUEMASU, Hiroyuki HIRANO, Masaaki ISHI
  • Patent number: 8652419
    Abstract: A method of manufacturing a microfluidic chip includes: irradiating, with a laser light, an area to be provided with a valley for storing a fluid on a surface of a substrate so as to form a modified region having a periodic pattern formed in a self-organizing manner in a light-collecting area of the laser light, the laser light having a pulse width for which the pulse duration is on the order of picoseconds or less; carrying out an etching treatment on the substrate in which the modified region is formed, removing at least some of the modified portion so as to provide the valley, and forming a periodic structure having a plurality of groove portions along one direction which have a surface profile based on the periodic pattern on at least a bottom surface of the valley; and forming a metal layer that covers the periodic structure of the bottom surface.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 18, 2014
    Assignee: Fujikura Ltd.
    Inventors: Satoshi Yamamoto, Tatsuo Suemasu
  • Patent number: 8564101
    Abstract: A semiconductor apparatus having a through-hole interconnection in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. A via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has another insulating layer formed in the via hole and a conductive layer formed thereon. The insulating layer formed in the via hole is formed such as to substantially planarize an inner surface of the via hole.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: October 22, 2013
    Assignees: Sony Corporation, Fujikura Ltd.
    Inventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
  • Patent number: 8273657
    Abstract: A method for manufacturing a semiconductor apparatus having a through-hole interconnection in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. A via hole is formed through the semiconductor substrate and the insulating layer. Another insulating layer is formed in the via hole, and a conductive layer of the through-hole interconnection is subsequently formed. The insulating layer formed in the via hole is formed such as to substantially planarize an inner surface of the via hole.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: September 25, 2012
    Assignees: Sony Corporation, Fujikura Ltd.
    Inventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
  • Publication number: 20110290545
    Abstract: A through wiring board provided with through wiring extending through the through hole of the board. The through wiring board comprises a through hole made through the board, through extension wiring provided in the through hole and extending on one side of the through wiring board up to a position at a predetermined distance from the through hole, and a conductive bump formed on the through extension wiring except the through hole position.
    Type: Application
    Filed: August 12, 2011
    Publication date: December 1, 2011
    Applicant: FUJIKURA LTD.
    Inventors: Hideyuki WADA, Tatsuo SUEMASU
  • Publication number: 20110136342
    Abstract: A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Applicants: SONY CORPORATION, FUJIKURA LTD
    Inventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
  • Patent number: 7814651
    Abstract: A blind hole (3) is formed on a substrate (1) from a first side of the substrate toward a second side of the substrate (1). A conductor (11) is filled in the blind hole (3). The substrate (1) is removed from the opposite side to expose the conductor (13) filled in the blind hole (3).
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: October 19, 2010
    Assignee: Fujikura Ltd.
    Inventors: Tatsuo Suemasu, Takashi Takizawa
  • Publication number: 20100117220
    Abstract: A semiconductor package includes at least: a workpiece at least one surface of which is equipped with a device; a wall portion provided along an outer circumference of the device and is spaced apart from the device; and a cover member that is arranged above the device so as to form a first space and is supported by the workpiece via the wall portion, in which the first space includes at least one second space that communicates with an external space.
    Type: Application
    Filed: January 15, 2010
    Publication date: May 13, 2010
    Applicant: FUJIKURA LTD.
    Inventors: Sayaka HIRAFUNE, Tatsuo SUEMASU
  • Publication number: 20090200679
    Abstract: A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate.
    Type: Application
    Filed: January 6, 2009
    Publication date: August 13, 2009
    Applicants: SONY CORPORATION, FUJIKURA LTD
    Inventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
  • Patent number: 7368321
    Abstract: A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically connected to the functional element via the first wiring; a through-hole interconnection that is electrically connected to the pad and is provided in a hole that is defined penetrating the semiconductor base material from the first side thereof to the second side thereof, the through-hole interconnection including a first insulating film and a first conductive material formed on the first insulating film; and a sealing material provided surrounding the functional element; a second substrate that is bonded to a first side of the first substrate via the sealing material.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: May 6, 2008
    Assignee: Fujikura Ltd.
    Inventors: Michikazu Tomita, Tatsuo Suemasu, Sayaka Hirafune
  • Publication number: 20070264753
    Abstract: A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically connected to the functional element via the first wiring; a through-hole interconnection that is electrically connected to the pad and is provided in a hole that is defined penetrating the semiconductor base material from the first side thereof to the second side thereof, the through-hole interconnection including a first insulating film and a first conductive material formed on the first insulating film; and a sealing material provided surrounding the functional element; a second substrate that is bonded to a first side of the first substrate via the sealing material.
    Type: Application
    Filed: July 26, 2007
    Publication date: November 15, 2007
    Applicant: FUJIKURA LTD.
    Inventors: Michikazu Tomita, Tatsuo Suemasu, Sayaka Hirafune
  • Patent number: 7274101
    Abstract: A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically connected to the functional element via the first wiring; a through-hole interconnection that is electrically connected to the pad and is provided in a hole that is defined penetrating the semiconductor base material from the first side thereof to the second side thereof, the through-hole interconnection including a first insulating film and a first conductive material formed on the first insulating film; and a sealing material provided surrounding the functional element; a second substrate that is bonded to a first side of the first substrate via the sealing material.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: September 25, 2007
    Assignee: Fujikura Ltd.
    Inventors: Michikazu Tomita, Tatsuo Suemasu, Sayaka Hirafune
  • Publication number: 20070187142
    Abstract: A blind hole (3) is formed on a substrate (1) from a first side of the substrate toward a second side of the substrate (1). A conductor (11) is filled in the blind hole (3). The substrate (1) is removed from the opposite side to expose the conductor (13) filled in the blind hole (3).
    Type: Application
    Filed: April 24, 2007
    Publication date: August 16, 2007
    Applicant: FUJIKURA LTD.
    Inventors: Tatsuo SUEMASU, Takashi Takizawa
  • Patent number: 7217890
    Abstract: A blind hole (3) is formed on a substrate (1) from a first side of the substrate toward a second side of the substrate (1). A conductor (11) is filled in the blind hole (3). The substrate (1) is removed from the opposite side to expose the conductor (13) filled in the blind hole (3).
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: May 15, 2007
    Assignee: Fujikura, Ltd.
    Inventors: Tatsuo Suemasu, Takashi Takizawa
  • Patent number: 7180149
    Abstract: A semiconductor package of the invention comprises: a semiconductor element provided with a circuit element on one surface of a semiconductor substrate; an external wiring region provided on an other surface of the semiconductor substrate; a support substrate disposed on the one surface of the semiconductor substrate; an electrode pad disposed on the one surface of the semiconductor substrate; and a through-electrode which extends from the electrode pad through to the other surface of the semiconductor substrate.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: February 20, 2007
    Assignees: Fujikura Ltd., Olympus Corporation
    Inventors: Satoshi Yamamoto, Tatsuo Suemasu, Sayaka Hirafune, Toshihiko Isokawa, Koichi Shiotani, Kazuya Matsumoto
  • Patent number: 7080560
    Abstract: The semiconductor pressure sensor includes a substrate (20). The sensor includes a diaphragm (26) implemented in the substrate (26) and being displaceable by a pressure medium acting on a side of the substrate (26). The sensor includes sensor circuitry (22, 23) implemented on the opposite side of the substrate in coincidence with the diaphragm (26) for detecting displacement of the diaphragm (26) for pressure.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: July 25, 2006
    Assignee: Fujikura Ltd.
    Inventors: Takashi Takizawa, Tatsuo Suemasu, Satoshi Yamamoto
  • Publication number: 20060113057
    Abstract: A metal filling process is provided in which micro holes formed in a work piece are filled with metal by immersing the work piece in molten metal and then removing the work piece from the molten metal. As the work piece is dipped into molten metal, a bottom surface of the work piece is tilted to an angle of 0.5° or more relative to the surface of the molten metal, and as the work piece is removed from the molten metal, a top surface of the work piece is tilted to an angle of 0.5° or more and less than 85° relative to the surface of the molten metal. Failures such as a work piece fracturing when it is dipped into molten metal, or when it is removed from molten metal, are prevented, and failures such as metal remaining on a surface of a work piece after the work piece has been removed from molten metal are also prevented.
    Type: Application
    Filed: January 18, 2006
    Publication date: June 1, 2006
    Inventors: Sayaka Hirafune, Tatsuo Suemasu
  • Patent number: 7022609
    Abstract: A manufacturing method of a semiconductor substrate provided with a through hole electrode is proposed. In accordance with the methods, it is possible to effectively form a through hole electrode in a semiconductor substrate in which a device and a wiring pattern have been already fabricated. This manufacturing method includes the steps of forming a first silicon oxide film 12 on a principal surface of the semiconductor substrate 11, forming a small hole 13 through the semiconductor substrate 11 from the opposite the step to reach to the first silicon oxide film 12, covering the inside of the small hole 13 with the second silicon oxide film 14, forming a first thin metal film 15 and a second thin metal film 16 on the first silicon oxide film 12, partially removing the first silicon oxide film 12 corresponding to the end of the small hole 13, and filling the small hole 13 with the conductive material to form a through hole electrode 17.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: April 4, 2006
    Assignees: Fujikura Ltd., Olympus Optical Co., Ltd.
    Inventors: Satoshi Yamamoto, Takashi Takizawa, Tatsuo Suemasu, Masahiro Katashiro, Hiroshi Miyajima, Kazuya Matsumoto, Toshihiko Isokawa
  • Publication number: 20060001147
    Abstract: A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically connected to the functional element via the first wiring; a through-hole interconnection that is electrically connected to the pad and is provided in a hole that is defined penetrating the semiconductor base material from the first side thereof to the second side thereof, the through-hole interconnection including a first insulating film and a first conductive material formed on the first insulating film; and a sealing material provided surrounding the functional element; a second substrate that is bonded to a first side of the first substrate via the sealing material.
    Type: Application
    Filed: June 27, 2005
    Publication date: January 5, 2006
    Inventors: Michikazu Tomita, Tatsuo Suemasu, Sayaka Hirafune
  • Publication number: 20050205997
    Abstract: A device having improved electrical connection includes a first substrate including a first side and a second side; a functional element on the first side of the first substrate; a pad that is electrically connected to the functional element; and a through-hole interconnection provided in a hole extending through the first substrate from the first side to the second side, the through-hole interconnection including a first conductive material and being electrically connected to the pad, and a conductive region that is provided along a portion of an inner surface of the hole, and is made of a second conductive material, different from the first conductive material.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 22, 2005
    Inventors: Satoshi Yamamoto, Tatsuo Suemasu