Patents by Inventor Tatsushi KANEDA
Tatsushi KANEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021585Abstract: A semiconductor device includes a plurality of transistors electrically connected to each other in parallel, the plurality of transistors respectively including first electrodes, a diode electrically connected in parallel to the plurality of transistors, the diode including an anode electrode, a first conductive pattern, a second conductive pattern electrically connected to the first conductive pattern, a plurality of first connection members directly connecting the first electrodes of the plurality of transistors to the first conductive pattern, respectively, and a second connection member connecting the anode electrode to the second conductive pattern. Each of the first electrodes is a source electrode or an emitter electrode. The plurality of transistors are arranged adjacent to each other.Type: ApplicationFiled: April 28, 2021Publication date: January 18, 2024Inventor: Tatsushi KANEDA
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Patent number: 11804465Abstract: A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.Type: GrantFiled: January 21, 2020Date of Patent: October 31, 2023Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Tatsushi Kaneda, Hirotaka Oomori, Ren Kimura, Toru Hiyoshi
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Publication number: 20230335413Abstract: A semiconductor device includes a first insulating substrate, a second insulating substrate, a first arm, a second arm connected to the first arm, and a first conductive pattern provided on the first insulating substrate. The first arm includes a plurality of first transistor chips provided on the first insulating substrate, and the second arm includes a semiconductor chip provided on the second insulating substrate. The plurality of first transistor chips are arranged adjacent to each other on the first insulating substrate, first electrodes of the plurality of first transistors are directly connected to the first conductive pattern, and each of the first electrodes is a source electrode or an emitter electrode.Type: ApplicationFiled: April 28, 2021Publication date: October 19, 2023Inventor: Tatsushi KANEDA
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Publication number: 20230335412Abstract: A semiconductor device includes a first insulating substrate, a second insulating substrate, a first transistor provided on the first insulating substrate, and a first diode provided on the second insulating substrate and connected in parallel to the first transistor.Type: ApplicationFiled: June 9, 2021Publication date: October 19, 2023Inventor: Tatsushi KANEDA
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Publication number: 20230326864Abstract: A semiconductor device includes a substrate, a circuit pattern, a P-terminal, an N-terminal, an O-terminal, a first transistor chip, a second transistor chip, a first diode chip, and a second diode chip. The circuit pattern includes a first region, a second region, and a third region. The third region includes a band-shaped first branch portion, a band-shaped second branch portion, and a connection portion. The first transistor chip is mounted on the first region. The second transistor chip is mounted on the second branch portion. The first diode chip is mounted on the first region. The second diode chip is mounted on the second branch portion. The first transistor chip and the first diode chip are disposed side by side along a first direction. The second transistor chip and the second diode chip are disposed side by side along the first direction.Type: ApplicationFiled: March 11, 2021Publication date: October 12, 2023Inventors: Tatsushi KANEDA, Hirotaka OOMORI
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Patent number: 11393733Abstract: A semiconductor device includes: a base plate having a first surface and having a first contact area in the first surface; a metal plate having a second surface, disposed such that the second surface faces the first surface, and having a second contact area in the second surface; a bonding material disposed between the first surface and the second surface and in contact with the first contact area and the second contact area to bond the metal plate and the base plate; an insulating plate disposed on the metal plate; a circuit member disposed on the insulating plate; a semiconductor element mounted to the circuit member; and a sealing material that covers the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor element to seal a space above the base plate, wherein outside the second contact area, the second surface has a non-contact area that is not in contact with the bonding material, wherein on the base plate, a groove portion facing the non-contact area and surType: GrantFiled: January 15, 2019Date of Patent: July 19, 2022Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Tatsushi Kaneda, Yoshisumi Kawabata, So Tanaka, Hirotaka Oomori
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Publication number: 20220130792Abstract: A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.Type: ApplicationFiled: January 21, 2020Publication date: April 28, 2022Applicant: Sumitomo Electric Industries, Ltd.Inventors: Tatsushi KANEDA, Hirotaka OOMORI, Ren KIMURA, Toru HIYOSHI
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Publication number: 20200395255Abstract: A semiconductor device includes: a base plate having a first surface and having a first contact area in the first surface; a metal plate having a second surface, disposed such that the second surface faces the first surface, and having a second contact area in the second surface; a bonding material disposed between the first surface and the second surface and in contact with the first contact area and the second contact area to bond the metal plate and the base plate; an insulating plate disposed on the metal plate; a circuit member disposed on the insulating plate; a semiconductor element mounted to the circuit member; and a sealing material that covers the metal plate, the bonding material, the insulating plate, the circuit member, and the semiconductor element to seal a space above the base plate, wherein outside the second contact area, the second surface has a non-contact area that is not in contact with the bonding material, wherein on the base plate, a groove portion facing the non-contact area and surType: ApplicationFiled: January 15, 2019Publication date: December 17, 2020Inventors: Tatsushi KANEDA, Yoshisumi KAWABATA, So TANAKA, Hirotaka OOMORI