Patents by Inventor Tatsuya Fujishima
Tatsuya Fujishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984484Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.Type: GrantFiled: September 9, 2021Date of Patent: May 14, 2024Assignee: Kioxia CorporationInventors: Tomonori Kajino, Taichi Iwasaki, Tatsuya Fujishima, Masayuki Shishido, Nozomi Kido
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Publication number: 20220310808Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.Type: ApplicationFiled: September 9, 2021Publication date: September 29, 2022Applicant: Kioxia CorporationInventors: Tomonori KAJINO, Taichi IWASAKI, Tatsuya FUJISHIMA, Masayuki SHISHIDO, Nozomi KIDO
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Patent number: 10777574Abstract: According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.Type: GrantFiled: March 12, 2019Date of Patent: September 15, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masayuki Shishido, Tatsuya Fujishima, Nozomi Kido, Tomonori Kajino
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Publication number: 20200091182Abstract: According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.Type: ApplicationFiled: March 12, 2019Publication date: March 19, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Masayuki SHISHIDO, Tatsuya FUJISHIMA, Nozomi KIDO, Tomonori KAJINO
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Publication number: 20200066748Abstract: According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of insulating layers and a plurality of conductive layers are alternately stacked above a substrate, a pillar that penetrates the stacked body while extending in a stacking direction of the stacked body, and a semiconductor layer, a first insulating layer, a charge accumulation layer, and a second insulating layer, which are stacked on a side surface of the pillar in order from the pillar, wherein the semiconductor layer has an average grain size that is larger on a side nearer to the pillar and is smaller on a side nearer to the first insulating layer.Type: ApplicationFiled: December 4, 2018Publication date: February 27, 2020Applicant: Toshiba Memory CorporationInventors: Daisuke MATSUSHITA, Yui KAGI, Tatsuya FUJISHIMA, Masayuki SHISHIDO, Nozomi KIDO, Tomonori KAJINO, Nobuhito KUGE
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Patent number: 10026743Abstract: A semiconductor memory device includes a stacked body including a plurality of word lines; a semiconductor layer extending through the word lines; a memory cell provided at a part where the semiconductor layer crosses one of the word lines, the memory cell including a plurality of cell layers, the cell layers including a first insulating layer; and at least one of a first structural body and a second structural body provided around the stacked body. The first structural body includes a plurality of monitor layers including same materials respectively as materials of the cell layers. The second structural body includes a first electrode, a second electrode and an insulating body positioned between the first electrode and the second electrode. The insulating body includes same material as a material of the first insulating layer, and has almost the same thickness as a thickness of the first insulating layer.Type: GrantFiled: November 16, 2016Date of Patent: July 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Nobuhito Kuge, Tatsuya Fujishima, Masayuki Shishido, Akira Kuramoto, Hideto Onuma
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Publication number: 20180047741Abstract: A semiconductor memory device includes a stacked body including a plurality of word lines; a semiconductor layer extending through the word lines; a memory cell provided at a part where the semiconductor layer crosses one of the word lines, the memory cell including a plurality of cell layers, the cell layers including a first insulating layer; and at least one of a first structural body and a second structural body provided around the stacked body. The first structural body includes a plurality of monitor layers including same materials respectively as materials of the cell layers. The second structural body includes a first electrode, a second electrode and an insulating body positioned between the first electrode and the second electrode. The insulating body includes same material as a material of the first insulating layer, and has almost the same thickness as a thickness of the first insulating layer.Type: ApplicationFiled: November 16, 2016Publication date: February 15, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Nobuhito KUGE, Tatsuya FUJISHIMA, Masayuki SHISHIDO, Akira KURAMOTO, Hideto ONUMA
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Patent number: 9337301Abstract: Semiconductor structures and techniques are described which enable forming aluminum nitride (AIN) based devices by confining carriers in a region of AIN by exploiting the polar nature of AIN materials. Embodiments of AIN transistors utilizing polarization-based carrier confinement are described.Type: GrantFiled: December 21, 2012Date of Patent: May 10, 2016Assignee: Massachusetts Institute of TechnologyInventors: Tomas Apostol Palacios, Tatsuya Fujishima
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Publication number: 20150028346Abstract: Semiconductor structures and techniques are described which enable forming aluminum nitride (AIN) based devices by confining carriers in a region of AIN by exploiting the polar nature of AIN materials. Embodiments of AIN transistors utilizing polarization-based carrier confinement are described.Type: ApplicationFiled: December 21, 2012Publication date: January 29, 2015Applicant: Massachusetts Institute of TechnologyInventors: Tomas Apostol Palacios, Tatsuya Fujishima
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Publication number: 20110125075Abstract: A method for controlling an electroporation apparatus for use in an animal such as human and a non-human animal, the method comprising a step of applying a voltage to an electrode of the electroporation apparatus placed in/on a biological sample of the animal in the presence of a nucleic acid construct capable of inhibiting the expression of a gene in the animal. In this manner, a nucleic acid construct can be introduced into a cell of a living body with good efficiency.Type: ApplicationFiled: July 14, 2006Publication date: May 26, 2011Applicant: National University Corporation Nagoya UniversityInventors: Yoshifumi Takei, Kenji Kadomatsu, Tatsuya Fujishima, Takashi Muramatsu
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Patent number: 7419874Abstract: The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.Type: GrantFiled: January 12, 2006Date of Patent: September 2, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Tatsuya Fujishima, Mikio Fukuda, Yuji Tsukada, Keiji Ogata, Izuo Iida
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Patent number: 7224038Abstract: A semiconductor device capable of preventing defective embedding of an insulator and improving the withstand voltage (dielectric strength) of an element isolation region is obtained. This semiconductor device comprises a semiconductor substrate having a main surface and an element isolation trench formed on the main surface of the semiconductor device, while the trench width of an upper end of the element isolation trench is larger than the trench width of a bottom surface and the length of a side surface located between the upper end and an end of the bottom surface is larger than the length of a straight line connecting the upper end and the end of the bottom surface. Thus, the element isolation trench is so formed that the trench width of the upper end is larger than the trench width of the bottom surface, whereby an insulator can be readily embedded in the element isolation trench. Thus, the insulator can be prevented from defective embedding.Type: GrantFiled: November 6, 2001Date of Patent: May 29, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Ryosuke Usui, Tatsuya Fujishima
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Publication number: 20060172488Abstract: The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.Type: ApplicationFiled: January 12, 2006Publication date: August 3, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tatsuya Fujishima, Mikio Fukuda, Yuji Tsukada, Keiji Ogata, Izuo Iida
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Patent number: 7066786Abstract: A method to quantitatively detect an optimum endpoint of dressing of a polishing pad with a non-destructive monitoring of a surface of the polishing pad is offered. The polishing pad is dressed for a predetermined period, and roughness of the surface of the polishing pad is measured with an optical measurement device made of a laser focus displacement meter. Then a characteristic curve representing a correlation between surface roughness of the polishing pad and dressing time is obtained. A gradient of the surface roughness versus dressing time characteristic curve is obtained. Dressing is stopped when the gradient reaches a predetermined value of gradient. These steps are repeated until the gradient of the surface roughness versus dressing time characteristic curve reaches the predetermined value of gradient.Type: GrantFiled: September 15, 2004Date of Patent: June 27, 2006Assignees: Sanyo Electric Co., Ltd., Rohm Co., Ltd.Inventors: Tatsuya Fujishima, Katsumi Sameshima
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Publication number: 20060113584Abstract: The first polysilicon film is formed on the semiconductor substrate with the gate insulation film between them. The second silicon nitride film with the first opening is further formed and the first polysilicon film is etched using the second silicon nitride film as a mask. Then, the spacer film with the second opening is formed at the first opening. The oxidation prevention layer is formed through the first anneal processing performed in ammonia atmosphere. Then, the source region, the source line, the source line cap film, the floating gate, the tunnel insulation film, the control gate, and the drain region are formed.Type: ApplicationFiled: November 7, 2005Publication date: June 1, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Mikio Fukuda, Tatsuya Fujishima
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Publication number: 20050090185Abstract: A method to quantitatively detect an optimum endpoint of dressing of a polishing pad with a non-destructive monitoring of a surface of the polishing pad is offered. The polishing pad is dressed for a predetermined period, and roughness of the surface of the polishing pad is measured with an optical measurement device made of a laser focus displacement meter. Then a characteristic curve representing a correlation between surface roughness of the polishing pad and dressing time is obtained. A gradient of the surface roughness versus dressing time characteristic curve is obtained. Dressing is stopped when the gradient reaches a predetermined value of gradient. These steps are repeated until the gradient of the surface roughness versus dressing time characteristic curve reaches the predetermined value of gradient.Type: ApplicationFiled: September 15, 2004Publication date: April 28, 2005Applicants: Sanyo Electric Co., Ltd., Rohm Co., Ltd.Inventors: Tatsuya Fujishima, Katsumi Sameshima
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Patent number: 6849550Abstract: A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.Type: GrantFiled: July 9, 2002Date of Patent: February 1, 2005Assignee: Sanyo Electric Co. Ltd.Inventors: Yoshinari Ichihashi, Norihiro Ikeda, Takashi Gotou, Ryousuke Usui, Tatsuya Fujishima
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Publication number: 20030060053Abstract: A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.Type: ApplicationFiled: July 9, 2002Publication date: March 27, 2003Inventors: Yoshinari Ichihashi, Norihiro Ikeda, Takashi Gotou, Ryousuke Usui, Tatsuya Fujishima
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Publication number: 20020056886Abstract: A semiconductor device capable of preventing defective embedding of an insulator and improving the withstand voltage (dielectric strength) of an element isolation region is obtained. This semiconductor device comprises a semiconductor substrate having a main surface and an element isolation trench formed on the main surface of the semiconductor device, while the trench width of an upper end of the element isolation trench is larger than the trench width of a bottom surface and the length of a side surface located between the upper end and an end of the bottom surface is larger than the length of a straight line connecting the upper end and the end of the bottom surface. Thus, the element isolation trench is so formed that the trench width of the upper end is larger than the trench width of the bottom surface, whereby an insulator can be readily embedded in the element isolation trench. Thus, the insulator can be prevented from defective embedding.Type: ApplicationFiled: November 6, 2001Publication date: May 16, 2002Applicant: Sanyo Electric Co.,Ltd.Inventors: Ryosuke Usui, Tatsuya Fujishima