Abstract: A test signal supplying device includes a first external terminal, a second external terminal being applied with a predetermined electric potential, an internal load, a first terminal that is connected to the first external terminal through the internal load, a second terminal that is connected to the first external terminal without passing through the internal load, a test signal generating section that generates a test signal and supplies the test signal to the second terminal, a detecting section that detects an amplitude of the test signal, and a controlling section that measures an impedance of an external load connected to the first and second external terminals based on the detected amplitude of the test signal.

Abstract: A power supply control circuit includes a mode controlling unit which, in accordance with an output voltage of an amplifying section, performs a mode up for switching a current power supply voltage of the amplifying section to a higher power supply voltage being higher than the current power supply voltage, and which, in a case where a magnitude of the output voltage of the amplifying section is smaller than a threshold voltage for a predetermined time period or longer, performs a mode down for switching the power supply voltage of the amplifying section to a lower power supply voltage being lower than the current power supply voltage, and a threshold setting unit which sets the threshold voltage based on the output voltage of the amplifying section at a timing when the mode up is performed.

Abstract: A test signal supplying device includes a first external terminal, a second external terminal being applied with a predetermined electric potential, an internal load, a first terminal that is connected to the first external terminal through the internal load, a second terminal that is connected to the first external terminal without passing through the internal load, a test signal generating section that generates a test signal and supplies the test signal to the second terminal, a detecting section that detects an amplitude of the test signal, and a controlling section that measures an impedance of an external load connected to the first and second external terminals based on the detected amplitude of the test signal.

Abstract: A power supply control circuit includes a mode controlling unit which, in accordance with an output voltage of an amplifying section, performs a mode up for switching a current power supply voltage of the amplifying section to a higher power supply voltage being higher than the current power supply voltage, and which, in a case where a magnitude of the output voltage of the amplifying section is smaller than a threshold voltage for a predetermined time period or longer, performs a mode down for switching the power supply voltage of the amplifying section to a lower power supply voltage being lower than the current power supply voltage, and a threshold setting unit which sets the threshold voltage based on the output voltage of the amplifying section at a timing when the mode up is performed.

Abstract: A class-D amplifier for generating from an input signal a digital signal for driving a load, includes an output limit instruction generating section that detects that the digital signal falls outside a limit range and that outputs an output limit instruction signal, an attenuation instruction pulse generating section that includes an integrator for integrating the output limit instruction signal and that outputs a periodical attenuation instruction pulse having pulse width corresponding to an integrated value in the integrator, an attenuating section provided in an input path for the input signal and that attenuates the input signal based on the attenuation instruction pulse, and a mute control section that controls the integrated value in the integrator independently of the output limit instruction signal to control an amount of the attenuation of the attenuating section applied to the input signal.

Abstract: A charge pump includes a switching circuit which is interposed among first and second output capacitors, a flying capacitor, and an input power supply; and a control unit which controls the switching circuit. The charge pump is operated in an operation mode including a high-voltage outputting mode, a low-voltage outputting mode, and a relay mode. The control unit controls the switching circuit so that respective charging voltages of the first and second capacitors that are charged in the high-voltage outputting mode are gradually lowered. The control unit changes the operation mode of the charge pump by relay transition from the high-voltage outputting mode through the relay mode to the low-voltage outputting mode when a voltage lower command is given during a period when the operation mode of the charge pump is in the high-voltage outputting mode.

Abstract: An amplifying device includes a selecting section that selects one of a first power source potential and a second power source potential which are different from each other, a potential generating circuit that generates a third power source potential from the power source potential selected by the selecting section, an amplifier that operates with supply of the first power source potential and the third power source potential, and a controlling circuit that variably controls a target to be selected by the selecting section in accordance with at least one of an amplitude of a signal on an input side of the amplifier, an amplitude of a signal on an output side of the amplifier, and the third power source potential.

Abstract: An amplifying device includes a selecting section that selects one of a first power source potential and a second power source potential which are different from each other, a potential generating circuit that generates a third power source potential from the power source potential selected by the selecting section, an amplifier that operates with supply of the first power source potential and the third power source potential, and a controlling circuit that variably controls a target to be selected by the selecting section in accordance with at least one of an amplitude of a signal on an input side of the amplifier, an amplitude of a signal on an output side of the amplifier, and the third power source potential.

Abstract: A charge pump includes a switching circuit which is interposed among first and second output capacitors, a flying capacitor, and an input power supply; and a control unit which controls the switching circuit. The charge pump is operated in an operation mode including a high-voltage outputting mode, a low-voltage outputting mode, and a relay mode. The control unit controls the switching circuit so that respective charging voltages of the first and second capacitors that are charged in the high-voltage outputting mode are gradually lowered. The control unit changes the operation mode of the charge pump by relay transition from the high-voltage outputting mode through the relay mode to the low-voltage outputting mode when a voltage lower command is given during a period when the operation mode of the charge pump is in the high-voltage outputting mode.

Abstract: A class-D amplifier for generating from an input signal a digital signal for driving a load, includes an output limit instruction generating section that detects that the digital signal falls outside a limit range and that outputs an output limit instruction signal, an attenuation instruction pulse generating section that includes an integrator for integrating the output limit instruction signal and that outputs a periodical attenuation instruction pulse having pulse width corresponding to an integrated value in the integrator, an attenuating section provided in an input path for the input signal and that attenuates the input signal based on the attenuation instruction pulse, and a mute control section that controls the integrated value in the integrator independently of the output limit instruction signal to control an amount of the attenuation of the attenuating section applied to the input signal.

Abstract: A differential amplifier includes: a constant current source; first and second field effect transistors whose respective gates are imparted with positive-phase and negative-phase input signals and whose sources commonly connected to each other, the constant current source being connected to a common node of the sources; first and second loads serving as current paths for respective drain currents of the first and second field effect transistors; an amplifying unit which outputs positive-phase and negative-phase output signals which are amplified in response to the respective drain voltages of the first and second field effect transistors; and a current path generator which generates first and second current paths parallel to the respective first and second field effect transistors for a predetermined period of time at the time of start-up of the differential amplifier.

Abstract: An offset correcting circuit includes: an amplifying unit including an offset adjusting unit that adjusts an offset of the amplifying unit; and an offset determining unit that that detects the offset of the amplifying unit outputs a signal for correcting the offset of the amplifying unit. The offset determining unit includes a comparing unit that compares an output of the amplifying unit with a reference value, and a counter that increases or decreases a count value in response to an output of the comparing unit. The offset adjusting unit adjusts the offset based on the count value and includes a bias varying portion for varying a bias of the amplifying unit based on the output of the counter.

Abstract: A differential amplifier includes: a constant current source; first and second field effect transistors whose respective gates are imparted with positive-phase and negative-phase input signals and whose sources commonly connected to each other, the constant current source being connected to a common node of the sources; first and second loads serving as current paths for respective drain currents of the first and second field effect transistors; an amplifying unit which outputs positive-phase and negative-phase output signals which are amplified in response to the respective drain voltages of the first and second field effect transistors; and a current path generator which generates first and second current paths parallel to the respective first and second field effect transistors for a predetermined period of time at the time of start-up of the differential amplifier.

Abstract: An offset correcting circuit includes: an amplifying unit including an offset adjusting unit that adjusts an offset of the amplifying unit; and an offset determining unit that that detects the offset of the amplifying unit outputs a signal for correcting the offset of the amplifying unit. The offset determining unit includes a comparing unit that compares an output of the amplifying unit with a reference value, and a counter that increases or decreases a count value in response to an output of the comparing unit. The offset adjusting unit adjusts the offset based on the count value and includes a bias varying portion for varying a bias of the amplifying unit based on the output of the counter.

Abstract: An offset correcting circuit includes: an amplifying unit including an offset adjusting unit that adjusts an offset of the amplifying unit; and an offset determining unit that outputs a signal to detect and corrects the offset of the amplifying unit. The offset determining unit includes a comparing unit that compares an output of the amplifying unit with a reference value, and a counter that increases or decreases a count value in response to an output of the comparing unit. The offset adjusting unit adjusts the offset based on the count value.

Abstract: An offset correcting circuit includes: an amplifying unit including an offset adjusting unit that adjusts an offset of the amplifying unit; and an offset determining unit that outputs a signal to detect and corrects the offset of the amplifying unit. The offset determining unit includes a comparing unit that compares an output of the amplifying unit with a reference value, and a counter that increases or decreases a count value in response to an output of the comparing unit. The offset adjusting unit adjusts the offset based on the count value.

Abstract: A pseudo-stereo circuit is provided which processes an input monophonic signal into stereophic audio signals. A phase-shift circuit shifts a phase of the input monophonic signal by a phase shift amount that depends upon a frequency of the monophonic signal, to produce an output signal having a gain with respect to the input monophonic signal which is equal to or larger than a predetermined level over an entire frequency band thereof, and reaches a peak at a frequency at which the phase shift amount of the output signal with respect to the input monophonic signal assumes a value equal or closer to −&pgr;. A mixing circuit produces a first mixed signal by mixing a signal obtained by inverting a phase of the output signal of the phase-shift circuit with the input monophonic signal by a first mixing ratio, and produces a second mixed signal obtained by mixing the output signal of the phase-shift circuit with the input monophonic signal by a second mixing ratio.

Abstract: The digital-to-analog conversion apparatus operates to convert an digital input into a corresponding analog output. A digital filter is provided for oversampling the digital input having a varying value represented in the form of multiple bits. A delta-sigma modulator operates to effect delta-sigma modulation of the oversampled digital input to reduce a number of the multiple bits for requantizing the oversampled digital input with a certain S/N ratio. A low-pass filter is provided for converting the requantized digital input into an analog output. A level detecting circuit is provided for detecting when the value of the digital input falls below a predetermined level. A shifting circuit is disposed upstream of the delta-sigma modulator and is responsive to the detected results for increasing the value of the digital input so as to improve the S/N ratio in the delta-sigma modulator.

Abstract: A sound field processor having amplitude/phase conversion circuits for left and right channels of a stereophonic signal. The amplitude/phase conversion circuits for left and right channels have substantially the same circuit structure. Each of the amplitude/phase conversion circuits has an inversion amplifier, an amplitude/phase characteristic changing circuit that changes amplitude and phase characteristics of an output from the inversion amplifier, and a feedback device that add outputs from the amplitude/phase characteristic changing circuit and outputs from the inversion amplifier to an input signal to generate a sum signal and feed back the sum signal to the inversion amplifier. An output from the inversion amplifier for the left channel and an output from the amplitude/phase characteristic changing circuit for the right channel are added by a first adder device.