Abstract: A semiconductor device includes a first electrode layer and a second electrode layer disposed over a substrate, a first insulating layer disposed over the first electrode layer, and a reflective electrode layer disposed on the first insulating layer and electrically connected to the first electrode layer, wherein the second electrode layer is exposed externally, and a thickness of the second electrode layer is greater than a thickness of the reflective electrode layer.

Abstract: A semiconductor device includes a first electrode layer and a second electrode layer disposed over a substrate, a first insulating layer disposed over the first electrode layer, and a reflective electrode layer disposed on the first insulating layer and electrically connected to the first electrode layer, wherein the second electrode layer is exposed externally, and a thickness of the second electrode layer is greater than a thickness of the reflective electrode layer.

Abstract: A method of fabricating a semiconductor device includes forming a first insulation film over a semiconductor substrate, the semiconductor substrate including an outer region and an inner region located at an inner side of the outer region, forming a first wiring over the first insulation film in the inner region, forming a second insulation film over the first wiring and over the first insulation film, decreasing a film thickness of the second insulation film in the inner region with regard to a film thickness of the second insulation film in the outer region, and polishing the second insulation film after the decreasing of the film thickness of the second insulation film.

Abstract: A method of fabricating a semiconductor device includes forming a first insulation film over a semiconductor substrate, the semiconductor substrate including an outer region and an inner region located at an inner side of the outer region, forming a first wiring over the first insulation film in the inner region, forming a second insulation film over the first wiring and over the first insulation film, decreasing a film thickness of the second insulation film in the inner region with regard to a film thickness of the second insulation film in the outer region, and polishing the second insulation film after the decreasing of the film thickness of the second insulation film.

Abstract: With the method for producing EPROMs based on selfalignment using a gate electrode as the mask for impurity ion doping, when selectively removing an oxide film between the control gate electrode and the floating gate electrode, the side surface of control gate electrode can be formed flat without projected and recessed areas by removing a thin film deposited at random on the side surface of the upper control gate electrode. Thus, the desired channel region width can be formed, even when impurity ions are doped, with the gate electrode used as the self-alignment mask. Controllability of EPROM production can, therefore, be remarkably improved.

Abstract: A semiconductor device having a multi-level interconnection structure includes an active device, a substrate supporting the active device thereon, and a first insulator layer provided so as to cover the substrate including the active device. A first conductor pattern is provided on the first insulator layer. A planarizing layer has a planarized top surface provided on the first insulator layer so as to bury the first conductor pattern underneath. A second insulator layer is provided on the planarized top surface of the planarizing layer. A contact hole is provided on the second insulator layer so as to expose a desired part of the first conductor pattern. A second conductor pattern is provided on the second insulator layer in correspondence to the contact hole so as to fill the contact hole and so as to make a contact to the exposed part of the first conductor pattern.

Abstract: A semiconductor device having a multi-level interconnection structure includes an active device, a substrate supporting the active device thereon, and a first insulator layer provided so as to cover the substrate including the active device. A first conductor pattern is provided on the first insulator layer. A planarizing layer has a planarized top surface provided on the first insulator layer so as to bury the first conductor pattern underneath. A second insulator layer is provided on the planarized top surface of the planarizing layer. A contact hole is provided on the second insulator layer so as to expose a desired part of the first conductor pattern. A second conductor pattern is provided on the second insulator layer in correspondence to the contact hole so as to fill the contact hole and so as to make a contact to the exposed part of the first conductor pattern.