Abstract: An operational amplifier circuit may include a fully differential amplifier circuit that has a common mode feedback, the fully differential amplifier circuit performing operational amplification using a common mode base voltage as a center, a common mode detection circuit that detects a common mode output voltage of the fully differential amplifier circuit, a sample and hold circuit that performs sample and hold of an output of the common mode detection circuit, an operational circuit that detects a deviation between the output of the sample and hold circuit and a common mode reference voltage, the operational circuit outputting a voltage corresponding to the detected deviation and the common mode reference voltage, and a switching circuit that selects the common mode reference voltage or an output of the operational circuit to output the common mode reference voltage or the output as the common mode base voltage.

Abstract: An amplifier circuit may include an input differential pair that includes a first transistor and a second transistor, a positive input voltage being supplied to a gate terminal of the first transistor, a negative input voltage being supplied to a gate terminal of the second transistor, a first resistor that generates a differential current corresponding to a differential voltage between the positive input voltage and the negative input voltage, an output differential pair that includes a third transistor and a fourth transistor, a negative output voltage being supplied from a drain terminal of the third terminal, a positive output voltage being supplied from a drain terminal of the fourth terminal, a second resistor that is connected to a reference voltage, the differential current generated by the first resistor being supplied to the second resistor, and a bias circuit that supplies a constant bias current to the first, second, third, and fourth transistors.

Abstract: An operational amplifier circuit may include a fully differential amplifier circuit that has a common mode feedback, the fully differential amplifier circuit performing operational amplification using a common mode base voltage as a center, a common mode detection circuit that detects a common mode output voltage of the fully differential amplifier circuit, a sample and hold circuit that performs sample and hold of an output of the common mode detection circuit, an operational circuit that detects a deviation between the output of the sample and hold circuit and a common mode reference voltage, the operational circuit outputting a voltage corresponding to the detected deviation and the common mode reference voltage, and a switching circuit that selects the common mode reference voltage or an output of the operational circuit to output the common mode reference voltage or the output as the common mode base voltage.

Abstract: A semiconductor device includes a MOS transistor switch that controls passage and interruption of a signal by switching between an ON state and an OFF state, a first switch connected between a back gate terminal of the MOS transistor switch and a source terminal of the MOS transistor switch, and a second switch connected between the back gate terminal of the MOS transistor switch and a power supply voltage terminal If the MOS transistor switch is in the ON state, the first switch is in the ON state and the back gate terminal of the MOS transistor switch is connected to the source terminal of the MOS transistor switch. If the MOS transistor switch is in the OFF state, the second switch is in the ON state, and the back gate terminal of the MOS transistor switch is connected to the power supply voltage terminal.

Abstract: An amplifier circuit may include an input differential pair that includes a first transistor and a second transistor, a positive input voltage being supplied to a gate terminal of the first transistor, a negative input voltage being supplied to a gate terminal of the second transistor, a first resistor that generates a differential current corresponding to a differential voltage between the positive input voltage and the negative input voltage, an output differential pair that includes a third transistor and a fourth transistor, a negative output voltage being supplied from a drain terminal of the third terminal, a positive output voltage being supplied from a drain terminal of the fourth terminal, a second resistor that is connected to a reference voltage, the differential current generated by the first resistor being supplied to the second resistor, and a bias circuit that supplies a constant bias current to the first, second, third, and fourth transistors.

Abstract: A flexible organic EL display of the present invention includes a plastic film, an adhesive layer and a lower insulating layer formed thereon, an organic EL element embedded in the lower insulating layer and constructed by forming an anode, an organic EL layer, and a cathode sequentially from a bottom, an upper insulating layer formed on the organic EL element, a TFT embedded in the upper insulating layer and constructed by forming an oxide semiconductor layer, a source electrode and a drain electrode, a gate insulating layer, and a gate electrode sequentially from a bottom, and a via hole provided in the upper insulating layer and reaching the drain electrode of the TFT, wherein the cathode is connected electrically to the drain electrode of the TFT via the via hole.

Abstract: A flexible organic EL display of the present invention includes a plastic film, an adhesive layer and a lower insulating layer formed thereon, an organic EL element embedded in the lower insulating layer and constructed by forming a cathode, an organic EL layer, and an anode sequentially from a bottom, an upper insulating layer formed on the organic EL element, a TFT embedded in the upper insulating layer and constructed by forming an organic active layer, a source electrode and a drain electrode, a gate insulating layer, and a gate electrode sequentially from a bottom, and a via hole provided in the upper insulating layer and reaching the drain electrode of the TFT, wherein the anode is connected electrically to the drain electrode of the TFT via the via hole.

Abstract: A signal processing apparatus includes an analog signal outputting circuit configured to output an analog signal divided into blocks in synchronization with a clock. An operation circuit is configured to operate in a clamping state to hold a reference signal and in a signal outputting state to output an effective signal by performing a specific operation on the analog signal with respect to the reference signal. A control circuit is configured to control the operation circuit and causes the operation circuit to operate in the clamping state longer than a period in which one block of the analog signal is output while the operation circuit remains in the signal outputting state.

Abstract: A focus detection device having a pair of light receiving sections (a first and second light receiving sections) which receive subject images observed from different view fields having parallax to accumulate charges is disclosed. The accumulation of the charges in the pair of light receiving sections is ended selectably based on an accumulation level of the charges at one light receiving section and an accumulation levels of the charges at both light receiving sections. Moreover/alternatively, the light receiving section has a plurality of light receiving units, and signals to end the accumulation of the charges at the respective light receiving units are sent to the first and second light receiving sections. In this case, a combination of the light receiving unit of the first light receiving section and the light receiving unit of the second light receiving section to which the signals are to be sent can be switched.

Abstract: There is disclosed a focus detection device having a light receiving section in which charges are generated and accumulated based on quantities of received lights and a charge accumulating section in which the charges accumulated in the light receiving section are transferred and accumulated. The focus detection device starts the accumulation of the charge in the light receiving section, when the charge accumulating section retains a reset state, and the device cancels the reset state of the charge accumulating section at a predetermined timing before the charges accumulated in the light receiving section are transferred to the accumulating section Moreover/alternatively, a focus detection device using a plurality of photo sensors is disclosed. A phase of a reading signal of a part of the photo sensors is different from that of a reading signal of another part.

Abstract: The present invention aims to solve problems involved in the formation of a conductive or insulating layer in a pattern form by photolithography, i.e., an environmental problem associated with handling of a solvent and a problem associated with wastewater treatment in the development with an aqueous alkaline solution. A method for forming a conductive layer (an anode bus 3) or an insulating layer (a barrier 1) on a glass substrate by photolithography using a photosensitive slurry solution prepared by mixing a low-melting glass powder as a binder and a conductive or insulating powder into a PVA-based, water-soluble photosensitive solution, wherein the content of B.sub.2 O.sub.3 component in the whole low-melting glass powder is closely regulated to not more than 6% by weight. This enables coating without gelation of PVA.