Patents by Inventor Tatsuya Urakawa
Tatsuya Urakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411051Abstract: A chip resistor includes an insulating substrate, a resistance element, and an electrode. The resistance element includes Cr, Si, and N and is disposed on the insulating substrate. The electrode includes at least one refractory metal and is disposed on the resistance element. An atomic ratio of Si to Cr in the resistance element is greater than or equal to ? and less than or equal to 4 at least at a center of the resistance element in a thickness direction defined with respect to the resistance element. An atom percentage of N in the resistance element is lower than or equal to 50 atom % at least at the center of the resistance element in the thickness direction.Type: ApplicationFiled: October 4, 2021Publication date: December 21, 2023Inventors: Daisuke SUETSUGU, Norimichi NOGUCHI, Tatsuya URAKAWA, Hiroki ODA, Daisuke UEYAMA
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Patent number: 11765824Abstract: A laminated ceramic sintered body board for an electronic device includes a ceramic sintered body board and a flattening film that is provided on an upper surface of the ceramic sintered body board and contains a thermally conductive filler, and the flattening film contains a thermally conductive filler.Type: GrantFiled: June 24, 2021Date of Patent: September 19, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Norimichi Noguchi, Masateru Mikami, Kenji Toyoshima, Hiroki Oda, Daisuke Suetsugu, Tatsuya Urakawa
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Publication number: 20220030707Abstract: A laminated ceramic sintered body board for an electronic device includes a ceramic sintered body board and a flattening film that is provided on an upper surface of the ceramic sintered body board and contains a thermally conductive filler, and the flattening film contains a thermally conductive filler.Type: ApplicationFiled: June 24, 2021Publication date: January 27, 2022Inventors: NORIMICHI NOGUCHI, MASATERU MIKAMI, KENJI TOYOSHIMA, HIROKI ODA, DAISUKE SUETSUGU, TATSUYA URAKAWA
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Patent number: 10048624Abstract: This conductive endless belt can suppress a reduction in toner releasability. The conductive endless belt is used in an image forming apparatus and includes at least an endless base layer and a surface layer formed on an outermost surface of an outer periphery of the base layer. The surface layer is formed from a resin composition including ultraviolet curable resin and silicone resin. The silicone resin includes polysiloxane containing, per molecule, 4 or more of at least one of an acryloyl group and a methacryloyl group.Type: GrantFiled: April 30, 2015Date of Patent: August 14, 2018Assignee: BRIDGESTONE CORPORATIONInventors: Takashi Ogura, Tatsuya Urakawa, Ryuuta Tanaka
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Publication number: 20180011181Abstract: A radar system includes a radar transceiver device, which includes a transmitter front end circuit for transmitting a chirp signal towards an object. The radar transceiver device includes a receiver front end circuit for receiving the reflected chirp signal from the object. The radar transceiver device includes a voltage controlled oscillator (VCO) to generate a transmitted chirp signal. The radar transceiver device includes a mixer configured to generate four intermediate frequency output signals having different phases. The radar system includes a controller device, which includes a processor, and a memory for storing the intermediate frequency output signals and instructions for executing in the processor. The instructions cause the processor to generate a complex Fast Fourier Transform (FFT) result by performing a FFT of the intermediate frequency output signals while using zero-padding.Type: ApplicationFiled: July 7, 2016Publication date: January 11, 2018Inventors: Tatsuya Urakawa, Abhiram Chakraborty, Masanobu Higuchi
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Publication number: 20170045845Abstract: This conductive endless belt can suppress a reduction in toner releasability. The conductive endless belt is used in an image forming apparatus and includes at least an endless base layer and a surface layer formed on an outermost surface of an outer periphery of the base layer. The surface layer is formed from a resin composition including ultraviolet curable resin and silicone resin. The silicone resin includes polysiloxane containing, per molecule, 4 or more of at least one of an acryloyl group and a methacryloyl group.Type: ApplicationFiled: April 30, 2015Publication date: February 16, 2017Applicant: BRIDGESTONE CORPORATIONInventors: Takashi OGURA, Tatsuya URAKAWA, Ryuuta TANAKA
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Patent number: 8922241Abstract: Provided is a logic circuit that can reduce the variation of a power supply voltage supplied thereto and a semiconductor integrated circuit including the logic circuit. The logic circuit includes a buffer unit, a voltage detection unit, and a switch unit. The buffer unit is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal. The voltage detection unit detects a voltage at the output terminal and outputs a detection signal based on a detection result. The switch unit connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal.Type: GrantFiled: September 11, 2012Date of Patent: December 30, 2014Assignee: Renesas Electronics CorporationInventor: Tatsuya Urakawa
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Patent number: 8766676Abstract: A down converter has two down converter circuits. The one down converter circuit has a first mixer, a first ½ frequency-divider, and a first PLL. The other down converter circuit has a second mixer, a second ½ frequency-divider, and a second PLL. A difference frequency between a frequency of a local oscillation frequency signal of the second PLL and a frequency of a frequency-divided signal of the first ½ frequency-divider is higher than an upper limit of a receive frequency band of a tuner.Type: GrantFiled: May 20, 2013Date of Patent: July 1, 2014Assignee: Renesas Electronics CorporationInventors: Yoshiaki Nakamura, Tatsuya Urakawa, Shigeya Suzuki, Jianqin Wang
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Publication number: 20130335124Abstract: A down converter has two down converter circuits. The one down converter circuit has a first mixer, a first ½ frequency-divider, and a first PLL. The other down converter circuit has a second mixer, a second ½ frequency-divider, and a second PLL. A difference frequency between a frequency of a local oscillation frequency signal of the second PLL and a frequency of a frequency-divided signal of the first ½ frequency-divider is higher than an upper limit of a receive frequency band of a tuner.Type: ApplicationFiled: May 20, 2013Publication date: December 19, 2013Applicant: Renesas Electronics CorporationInventors: Yoshiaki NAKAMURA, Tatsuya URAKAWA, Shigeya SUZUKI, Jianqin WANG
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Publication number: 20130082734Abstract: Provided is a logic circuit that can reduce the variation of a power supply voltage supplied thereto and a semiconductor integrated circuit including the logic circuit. The logic circuit includes a buffer unit, a voltage detection unit, and a switch unit. The buffer unit is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal. The voltage detection unit detects a voltage at the output terminal and outputs a detection signal based on a detection result. The switch unit connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal.Type: ApplicationFiled: September 11, 2012Publication date: April 4, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuya URAKAWA
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Publication number: 20110085625Abstract: A receiver includes an automatic gain control (AGC) loop and a filter group that is arranged downstream of the AGC loop. The filter group includes an active filter. The receiver further includes a power difference detector and a switch circuit. The power difference detector detects a power difference between intermediate and output nodes of the filter group to detect presence of an interference wave that is different from a desired wave and that has a frequency near that of the desired wave. The switch circuit switches an operation to suppress a convergence power of the AGC loop when the power difference detector detects the interference wave.Type: ApplicationFiled: October 12, 2010Publication date: April 14, 2011Applicant: Renesas Electronics CorporationInventors: Tatsuya URAKAWA, Noriaki Matsuno
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Patent number: 7292119Abstract: The phase locked loop frequency synthesizer, includes: an LC-tank circuit which includes an inductor and a variable capacitor in which the capacity changes depending on the input voltage; a group of fixed-value capacitors which is connected to the LC-tank circuit in parallel; a voltage control oscillating unit which outputs a signal with a frequency determined by the LC-tank circuit and the group of fixed-value capacitors; a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of the frequency output from the voltage control oscillating unit; a fixed-value capacitor controlling unit which outputs a selection signal which determines the combination of the fixed-value capacitors to be connected to the LC-tank circuit in parallel based on a frequency dividing ratio setting signal including information about dividing ratio of the second signal, and controls the connectioType: GrantFiled: March 24, 2005Date of Patent: November 6, 2007Assignee: NEC Electronics CorporationInventor: Tatsuya Urakawa
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Publication number: 20050219003Abstract: The phase locked loop frequency synthesizer, includes: an LC-tank circuit which includes an inductor and a variable capacitor in which the capacity changes depending on the input voltage; a group of fixed-value capacitors which is connected to the LC-tank circuit in parallel; a voltage control oscillating unit which outputs a signal with a frequency determined by the LC-tank circuit and the group of fixed-value capacitors; a phase control unit which generates an output current based on an error operator between a first signal with a divided frequency of a reference frequency and a second signal with a divided frequency of the frequency output from the voltage control oscillating unit; a fixed-value capacitor controlling unit which outputs a selection signal which determines the combination of the fixed-value capacitors to be connected to the LC-tank circuit in parallel based on a frequency dividing ratio setting signal including information about dividing ratio of the second signal, and controls the connectioType: ApplicationFiled: March 24, 2005Publication date: October 6, 2005Applicant: NEC Compound Semiconductor Devices, Ltd.Inventor: Tatsuya Urakawa