Patents by Inventor Tatsuzo Kawaguchi

Tatsuzo Kawaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8247289
    Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: August 21, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kinji Yamada, Tomotaka Shinoda, Katsuya Okumura, Shuichi Kawano
  • Patent number: 7742277
    Abstract: A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: June 22, 2010
    Assignee: Ibiden Company Limited
    Inventors: Tomotaka Shinoda, Kinji Yamada, Takahiro Kitano, Yoshiki Yamanishi, Muneo Harada, Tatsuzo Kawaguchi, Yoshihiro Hirota, Katsuya Okumura, Shuichi Kawano
  • Publication number: 20070181928
    Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.
    Type: Application
    Filed: August 23, 2006
    Publication date: August 9, 2007
    Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kinji Yamada, Tomotaka Shinoda, Katsuya Okumura, Shuichi Kawano
  • Publication number: 20070181556
    Abstract: Atmosphere in processing apparatus is adjusted to, for example, oxygen atmosphere, by gas supply source and the like. Interior of thermal processing apparatus is set to oxygen atmosphere and raised to predetermined temperature. A wafer boat containing wafer W having dielectric precursor layer formed is loaded into thermal processing apparatus at speed at which no defects are produced in wafer W. Thereafter, reaction tube of thermal processing apparatus has its internal temperature raised to baking temperature, to perform baking for predetermined time. The wafer W is cooled to predetermined temperature in thermal processing apparatus and then to room temperature in processing apparatus, and carried out from processing apparatus.
    Type: Application
    Filed: August 23, 2006
    Publication date: August 9, 2007
    Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kenji Matsuda, Kinji Yamada, Tomotaka Shinoda, Daohai Wang, Katsuya Okumura
  • Publication number: 20070126041
    Abstract: A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.
    Type: Application
    Filed: August 23, 2006
    Publication date: June 7, 2007
    Applicants: TOKYO ELECTRON LIMITED, Ibiden Company Limited, OCTEC Incorporated
    Inventors: Tomotaka Shinoda, Kinji Yamada, Takahiro Kitano, Yoshiki Yamanishi, Muneo Harada, Tatsuzo Kawaguchi, Yoshihiro Hirota, Katsuya Okumura, Shuichi Kawano
  • Patent number: 5733427
    Abstract: A sputtering target formed of a refractory metallic silicide having a composition MSi.sub.x including a mixture composition of an MSi.sub.2 phase in the form of particles (M: at least one refractory metal selected from a group consisting of W, Mo, Ti, Zr, Hf, Ni and Ta), and an Si phase provided as a matrix phase. Interface layers having a predetermined thickness are formed at the interfaces between the MSi.sub.2 phase and the Si phase. The value X in the composition formula MSi.sub.x is set to a range of 2.0 to 4.0, and the thickness of the interface layers formed between the MSi.sub.2 phase and the Si phase, the dispersion of the composition, the density ratio of the target, the electrical resistivity of the Si phase and the surface roughness are set to predetermined values. An uniform high-quality thin film in which a composition distribution is uniform can be manufactured stably by using this target.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: March 31, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michio Satou, Takashi Yamanobe, Mitsuo Kawai, Tatsuzo Kawaguchi, Kazuhiko Mitsuhashi, Toshiaki Mizutani
  • Patent number: 5447616
    Abstract: A sputtering target formed of a refractory metallic silicide having a composition MSi.sub.x including a mixture composition of an MSi.sub.2 phase in the form of particles (M: at least one refractory metal selected from a group consisting of W, Mo, Ti, Zr, Hf, Ni and Ta), and an Si phase provided as a matrix phase. Interface layers having a predetermined thickness are formed at the interfaces between the MSi.sub.2 phase and the Si phase. The value X in the composition formula MSi.sub.x is set to a range of 2.0 to 4.0, and the thickness of the interface layers formed between the MSi.sub.2 phase and the Si phase, the dispersion of the composition, the density ratio of the target, the electrical resistivity of the Si phase and the surface roughness are set to predetermined values. An uniform high-quality thin film in which a composition distribution is uniform can be manufactured stably by using this target.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: September 5, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michio Satou, Takashi Yamanobe, Mitsuo Kawai, Tatsuzo Kawaguchi, Kazuhiko Mitsuhashi, Toshiaki Mizutani
  • Patent number: 5294321
    Abstract: A sputtering target formed of a refractory metallic silicide having a composition MSi.sub.x including a mixture composition of an MSi.sub.2 phase in the form of particles (M: at least one refractory metal selected from a group consisting of W, Mo, Ti, Zr, Hf, Ni and Ta), and an Si phase provided as a matrix phase. Interface layers having a predetermined thickness are formed at the interfaces between the MSi.sub.2 phase and the Si phase. The value X in the composition formula MSi.sub.x is set to a range of 2.0 to 4.0, and the thickness of the interface layers formed between the MSi.sub.2 phase and the Si phase, the dispersion of the composition, the density ratio of the target, the electrical resistivity of the Si phase and the surface roughness are set to predetermined values. An uniform high-quality thin film in which a composition distribution is uniform can be manufactured stably by using this target.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: March 15, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michio Satou, Takashi Yamanobe, Mitsuo Kawai, Tatsuzo Kawaguchi, Kazuhiko Mitsuhashi, Toshiaki Mizutani
  • Patent number: 4485000
    Abstract: In a sputtering target supporting device for fixing, to a common electrode, a plurality of beams forming a mosaic target used for co-sputtering, at least one pressing mechanism is provided exclusively for each of the beams to press the respective beam against the common electrode by means of the respective pressing mechanism provided therefor.
    Type: Grant
    Filed: April 25, 1984
    Date of Patent: November 27, 1984
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuzo Kawaguchi, Mitsutoshi Koyama