Patents by Inventor Tatsuzo Kawaguchi
Tatsuzo Kawaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8247289Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.Type: GrantFiled: August 23, 2006Date of Patent: August 21, 2012Assignee: Ibiden Co., Ltd.Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kinji Yamada, Tomotaka Shinoda, Katsuya Okumura, Shuichi Kawano
-
Patent number: 7742277Abstract: A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.Type: GrantFiled: August 23, 2006Date of Patent: June 22, 2010Assignee: Ibiden Company LimitedInventors: Tomotaka Shinoda, Kinji Yamada, Takahiro Kitano, Yoshiki Yamanishi, Muneo Harada, Tatsuzo Kawaguchi, Yoshihiro Hirota, Katsuya Okumura, Shuichi Kawano
-
Publication number: 20070181928Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.Type: ApplicationFiled: August 23, 2006Publication date: August 9, 2007Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kinji Yamada, Tomotaka Shinoda, Katsuya Okumura, Shuichi Kawano
-
Publication number: 20070181556Abstract: Atmosphere in processing apparatus is adjusted to, for example, oxygen atmosphere, by gas supply source and the like. Interior of thermal processing apparatus is set to oxygen atmosphere and raised to predetermined temperature. A wafer boat containing wafer W having dielectric precursor layer formed is loaded into thermal processing apparatus at speed at which no defects are produced in wafer W. Thereafter, reaction tube of thermal processing apparatus has its internal temperature raised to baking temperature, to perform baking for predetermined time. The wafer W is cooled to predetermined temperature in thermal processing apparatus and then to room temperature in processing apparatus, and carried out from processing apparatus.Type: ApplicationFiled: August 23, 2006Publication date: August 9, 2007Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kenji Matsuda, Kinji Yamada, Tomotaka Shinoda, Daohai Wang, Katsuya Okumura
-
Publication number: 20070126041Abstract: A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.Type: ApplicationFiled: August 23, 2006Publication date: June 7, 2007Applicants: TOKYO ELECTRON LIMITED, Ibiden Company Limited, OCTEC IncorporatedInventors: Tomotaka Shinoda, Kinji Yamada, Takahiro Kitano, Yoshiki Yamanishi, Muneo Harada, Tatsuzo Kawaguchi, Yoshihiro Hirota, Katsuya Okumura, Shuichi Kawano
-
Patent number: 5733427Abstract: A sputtering target formed of a refractory metallic silicide having a composition MSi.sub.x including a mixture composition of an MSi.sub.2 phase in the form of particles (M: at least one refractory metal selected from a group consisting of W, Mo, Ti, Zr, Hf, Ni and Ta), and an Si phase provided as a matrix phase. Interface layers having a predetermined thickness are formed at the interfaces between the MSi.sub.2 phase and the Si phase. The value X in the composition formula MSi.sub.x is set to a range of 2.0 to 4.0, and the thickness of the interface layers formed between the MSi.sub.2 phase and the Si phase, the dispersion of the composition, the density ratio of the target, the electrical resistivity of the Si phase and the surface roughness are set to predetermined values. An uniform high-quality thin film in which a composition distribution is uniform can be manufactured stably by using this target.Type: GrantFiled: March 30, 1995Date of Patent: March 31, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Michio Satou, Takashi Yamanobe, Mitsuo Kawai, Tatsuzo Kawaguchi, Kazuhiko Mitsuhashi, Toshiaki Mizutani
-
Patent number: 5447616Abstract: A sputtering target formed of a refractory metallic silicide having a composition MSi.sub.x including a mixture composition of an MSi.sub.2 phase in the form of particles (M: at least one refractory metal selected from a group consisting of W, Mo, Ti, Zr, Hf, Ni and Ta), and an Si phase provided as a matrix phase. Interface layers having a predetermined thickness are formed at the interfaces between the MSi.sub.2 phase and the Si phase. The value X in the composition formula MSi.sub.x is set to a range of 2.0 to 4.0, and the thickness of the interface layers formed between the MSi.sub.2 phase and the Si phase, the dispersion of the composition, the density ratio of the target, the electrical resistivity of the Si phase and the surface roughness are set to predetermined values. An uniform high-quality thin film in which a composition distribution is uniform can be manufactured stably by using this target.Type: GrantFiled: December 14, 1993Date of Patent: September 5, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Michio Satou, Takashi Yamanobe, Mitsuo Kawai, Tatsuzo Kawaguchi, Kazuhiko Mitsuhashi, Toshiaki Mizutani
-
Patent number: 5294321Abstract: A sputtering target formed of a refractory metallic silicide having a composition MSi.sub.x including a mixture composition of an MSi.sub.2 phase in the form of particles (M: at least one refractory metal selected from a group consisting of W, Mo, Ti, Zr, Hf, Ni and Ta), and an Si phase provided as a matrix phase. Interface layers having a predetermined thickness are formed at the interfaces between the MSi.sub.2 phase and the Si phase. The value X in the composition formula MSi.sub.x is set to a range of 2.0 to 4.0, and the thickness of the interface layers formed between the MSi.sub.2 phase and the Si phase, the dispersion of the composition, the density ratio of the target, the electrical resistivity of the Si phase and the surface roughness are set to predetermined values. An uniform high-quality thin film in which a composition distribution is uniform can be manufactured stably by using this target.Type: GrantFiled: November 10, 1993Date of Patent: March 15, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Michio Satou, Takashi Yamanobe, Mitsuo Kawai, Tatsuzo Kawaguchi, Kazuhiko Mitsuhashi, Toshiaki Mizutani
-
Patent number: 4485000Abstract: In a sputtering target supporting device for fixing, to a common electrode, a plurality of beams forming a mosaic target used for co-sputtering, at least one pressing mechanism is provided exclusively for each of the beams to press the respective beam against the common electrode by means of the respective pressing mechanism provided therefor.Type: GrantFiled: April 25, 1984Date of Patent: November 27, 1984Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuzo Kawaguchi, Mitsutoshi Koyama